我刚好在看ICH8 datasheet,其中% u4 Y. H' E5 ]; O# I: }2 u0 f1 H( U
PM1_STS—Power Management 1 Status Register ( i' J5 ~) U: N! Q
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an : ~- D3 h8 }2 b# z: y/ H+ d# |SMI# or SCI. 4 j+ [. _1 L5 i: P- \建议在DATASHEET中搜索一下SMI : g6 t( h& I2 o! ~0 A0 Y- Y6 X2 o6 j# z }+ p" V7 K
[ 本帖最后由 jackey_gu 于 2008-7-15 16:24 编辑 ]
可以把software smi value写入一个特定SMI TRAP IO端口来产生SW SMI。对于intel chipset来说,这个端口一般是0B2h。 ; C: p4 @) I5 h0 [% G2 q: d. ~ich7 spec里摘出的: ( a% w$ L9 U5 J9 M$ j; S: d----------------------------------------/ f6 j- M6 n6 k% m9 F% M
APM_CNT—Advanced Power Management Control Port Register- |: c+ G" ^( z4 L: y
I/O Address: B2h Attribute: R/W $ s' S$ L5 J: G& U& `8 `Default Value: 00h Size: 8-bit $ }. w) `# V* @ n' X7 E0 xLockable: No Usage: Legacy Only7 Y: w( Z5 _: c. n9 f
Power Well: Core ) q* v+ b( G0 KBit Description4 l: v$ j- A& S) P9 u- {. m
7:0 % P k# E7 J# m* k# x! dUsed to pass an APM command between the OS and the SMI handler. Writes to this3 q7 b& \( Q$ ?+ p6 t
port not only store data in the APMC register, but also generates an SMI# when the " p$ x q$ Q9 G: d) i5 Q: [8 w! h. xAPMC_EN bit is set.) L( M1 ~8 n$ S! i3 T: V6 F9 o
--------------------------------------- ( g& n: H$ q- ]# y2 G! z 9 i6 m) b8 N+ D6 l ` i[ 本帖最后由 alanzhu 于 2008-7-15 16:57 编辑 ]