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Feature Summary
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Low Pin Count Host Interface (LPC)
% |' s! M6 I. x$ o* a SIRQ supporting IRQ1, IRQ12, SCI
; |6 t6 ^* c X& S3 G I/O Address Decoding:
. D2 q& l; E! ]6 y# a# g KBC IO Port 60h/64h0 h9 V: P$ n% w1 h: V0 w' E( B; ?
Programmable EC IO Port 62h/66h and 68h/6Ch2 y4 R } k. S$ o* U* x" x _
Programmable 4-byte Index I/O ports to access internal registers
; I3 z& `& r* g4 t One Programmable I/O write byte-address decoding
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$ _( {) n9 Z3 `X-Bus Interface (XBI)
- P! B9 `1 d* w' Q% i9 \# G SPI Flash support, the operation frequency runs at least 50MHz.: B! M& e F# T
Addressable Memory range up to 24MB.
7 a! [6 s+ m' r# F& G [, | 8051 64KB code memory can be mapped into 4 independent 16KB pages.
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8051 Microprocessor* }/ L+ s9 e( R5 I4 b6 ` X
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
3 ]+ t+ J5 E/ _ Programmable 8/16/32 MHz clock) g* [; D( H5 o L' ?* M
Fast instruction fetching from XBI Interface+ n4 n- X+ W, J2 V$ u+ q6 Q
128 bytes and 2KB tightly-coupled SRAM
3 \7 |% M4 E, C1 S6 E! J; S. m" L 24 extended interrupt sources.
% M; G/ f; v) \! c8 |( [5 t Two 16-bit tightly-coupled timer+ ]8 }, S6 }( @" Y$ I8 G |- H6 q
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8042 Keyboard Controller7 u2 @$ e4 ]6 q
8 Standard keyboard commands processed by hardware
" A% |3 ?: ^4 x% C- ^: {: D Each hardware command can be optionally processed by firmware
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; a2 \. j* W' REmbedded Controller (EC)
0 P6 S; j9 Z' L5 \- S Five EC Standard Commands can be processed by hardware
: v, L M* Q! b ACPI Specification 2.0 compliant
( A2 h! s8 G2 d5 K8 _; z Support customer command by firmware+ j- v* A9 @ X3 G1 d8 W; `
Programmable EC I/O port addressing (default 62h/66h)
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Analog To Digital Converter (ADC)
0 s- w4 @' ^# o V( R5 R 6 built-in ADCs with 8-bit resolution.
: C1 X9 X3 s# }% ^ The ADC pins can be alternatively configured as General Purpose Inputs (GPI).& h/ }) Y0 o2 G5 R, `. S$ r
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Pulse Width Modulator (PWM)
& B9 E- L4 f i: C 5 built-in PWMs7 a4 D; b0 E* H4 r
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz. e! p# v1 g+ u6 N$ B4 o! G' [
Configurable cycle time (up to 1 sec) and duty cycle.$ t5 w' w b* `5 ~8 S
" [+ c- W3 I" y$ o# `Watchdog Timer (WDT)- ]* m4 }. p' x1 v; t* E/ r
32.768KHz input clock with 20-bit time scale.
( |' @7 }% R5 G1 {) ` 8-bit watchdog timer interrupt and reset setting
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General Purpose Timer (GPT)
; s M; q" h' D0 X0 P2 i7 E1 J) f Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution, @3 i& S1 O( C( ^" {) o! h( H
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General Purpose Wake-Up (GPWU)
# o) O. _6 B4 r3 F All General Purpose Input pins can be configured to generate interrupts or wake-up event.2 ?: s' r8 C8 N
1 h8 F$ d) Q* M/ v' y* o4 EGeneral Purpose Input/Output (GPIO)4 ^8 u* \5 k9 b2 n# r$ E
All I/O pins are bi-direction and configurable
/ R' _! _" W3 j1 ?# E" z0 m All outputs can be optionally tri-stated
. P! h w5 j1 q) g- n* u$ v All inputs equipped with pull-up, high/low active, edge/level trigger selection! l. h! E& f) ~$ x
All GPIO pins are bi-direction, input and output.: E s& T7 G! E! G8 M0 P
Max. 43 GPIOs
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8 _# ^3 Q& b, e5 Q. W1 ]. b- l$ mPower Management
$ x- H: x) L0 W9 _1 r* i4 l E7 M) h Sleep State: 8051 Program Counter (PC) stopped' ^9 ~: E7 f: E& N
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.5 e2 ^; P: S$ J& L: C+ f
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