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URL Link: http://www.intel.com/technology/framework/spec.htm
7 s2 x4 n" n7 h7 y/ A0 t, k3 s1 `The Intel® Platform Innovation Framework for EFI Architecture Specification describes the primary design elements of an innovative approach to constructing platform firmware for platforms based on Intel® architecture. The design is characterized by a central “framework” that provides services and infrastructure to combine modular software building block elements. Taken together, the infrastructure code—which is known as the Foundations—and an appropriate selection of modular building blocks constitute a complete platform software implementation that is designed to initialize the platform and boot shrink-wrap operating systems or other custom application environments. The Foundations are comprised of the Pre-EFI Initialization (PEI) and Driver Execution Environment (DXE) phases, which are both described in this specification. In addition, this specification describes a number of other design elements in an effort to provide a complete set of baseline design and services support for arbitrary building blocks that will customize a particular platform firmware image to the hardware and the intended purpose and market for that hardware. These additional elements include such things as security services, boot device policy management, runtime services, afterlife, firmware storage, user interface, firmware integrity services, manageability support, legacy compatibility and boot/resume paths. ( l0 B) e" F. y, s# R
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Interoperability and Component Specifications * l6 Q. a" }" K3 _' T
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These additional specifications describe in greater depth the functional components that complement the PEI and DXE Foundations and that are also architectural in the Framework design. "Architectural" in this context implies that the functional components provide services that may always be assumed to be present by any code designed and written to operate across a range of platforms that use firmware based on the Framework design. / {7 O9 L' \ A1 u# b, X+ z
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All specifications are available as PDF files `# ~- u) d4 [! e. ?
& c0 E4 q" h$ \; cZip file containing all PDF files (ZIP 11MB)) p I8 @" {/ i$ I
Include: A% X% a/ z. G+ A
Intel® Platform Innovation Framework for EFI Architecture Specification (PDF 893KB)
. M+ c: a( o, g) ~; _# p1 z8 NACPI Specification v0.90 (PDF 212KB) " z" b! O1 v( q. C
ACPI Specification v0.91 (PDF 246KB) - V) V8 | g7 a: F# f5 }9 b' b
ACPI Table Storage Specification v0.90 (PDF 139KB)
% }3 \$ X" ~; Q JACPI Table Storage Specification v0.91 (PDF 190KB)
! a$ }8 D! ~9 I, w! zBoot Script Specification v0.9 (PDF 200KB)
; _8 S. P! Z& R! iBoot Script Specification v0.91 (PDF 275KB) + a; Y* A4 A! U( ^ ` F
Cache Subclass Specification (PDF 224KB) - @. {/ e+ {( f) w
Capsule Specification (PDF 270KB) 5 j1 s& a2 i7 e0 d
Compatibility Support Module Specification v0.96 (PDF 547KB) 9 y& I, {2 P8 Y! w) [
Compatibility Support Module Specification v0.97 (PDF 576KB)
0 e) E/ m9 e3 h8 m1 d8 }CPU I/O Protocol Specification (PDF 205KB) . p! f" n& A0 ~4 V. p3 `
Data Hub Specification (PDF 177KB) ' r9 o8 S# ^1 T5 ]- `
Data Hub Subclass Design Guide (PDF 156KB) 5 U6 |; I( v1 f2 e* S% q& P3 W% e
Driver Execution Environment Core Interface Specification (DXE CIS)** v0.9 (PDF 1.05MB)
( N$ T( S8 v- q; K, uDriver Execution Environment Core Interface Specification (DXE CIS)** v0.91 (PDF 1.07MB)
. v# h e9 C* U" w) ?% mFirmware File System Specification (PDF 237KB) 7 k9 E# d/ ]" ~
Firmware Volume Block Specification (PDF 197KB) 5 l1 a; f7 I+ V* L* s& Z5 u
Firmware Volume Specification (PDF 403KB) : \- R. Z5 q v; Y8 r
Hand-Off Block (HOB) Specification (PDF 231KB)
+ s I$ x9 Z& H- i% `* X. Y9 NHot-Plug PCI Initialization Protocol Specification (PDF 108KB) - W# v# A0 V( K: u4 g J
Human Interface Infrastructure Specification v0.9 (PDF 597KB) 6 s& F( Y' r. t0 Q( I4 o
Human Interface Infrastructure Specification v0.91 (PDF 800KB)
2 P9 @, W( F: U7 g8 pHuman Interface Infrastructure Specification v0.92 (PDF 764KB)
9 N8 s4 ~; h5 O" q ~: ZIDE Controller Initialization Protocol Specification (PDF 139KB) ( K+ C- J0 N2 e8 O9 _. t0 \) V% R
Memory Subclass Specification (PDF 397KB) 6 S5 D% l P1 F0 t! L6 }+ d
Miscellaneous Subclass Specification (PDF 490KB)
" Y+ t v5 P7 f" h- I: Z* [8 ZPCI Host Bridge Resource Allocation Protocol Specification (PDF 212KB)
" }) T# Q! d6 CPCI Platform Support Specification (PDF 115KB)
* |6 I ~& j6 B) l/ NPlatform IDE Initialization Protocol Specification (PDF 83KB)
- r# O3 |- G2 c$ PPre-EFI Initialization Core Interface Specification (PEI CIS)** v0.9 (PDF 881KB) 7 |' L" J7 z/ z' E5 z
Pre-EFI Initialization Core Interface Specification (PEI CIS)** v0.91 (PDF 841KB)
8 r1 R7 N6 J2 z% [5 {Processor Subclass Specification (PDF 314KB)
, P5 K% ^/ m& U1 ^# g) VRecovery Specification (PDF 225KB)
2 M" k# Z3 h/ JS3 Resume Boot Path Specification (PDF 173KB) 4 ~& l( q9 q( v y
SMBus Host Controller Protocol Specification (PDF 198KB)
) ^% `# F, n* e0 ZSMBus PPI Specification (PDF 188KB)
2 u9 I/ |$ x& U8 H6 c5 ?Status Codes Specification v0.9 (PDF 682KB)
q8 W$ K G2 k, }Status Codes Specification v0.92 (PDF 523KB)
3 X, w4 L( b6 @System Management Mode Core Interface Specification (SMM CIS) v0.9 (PDF 713KB) . z" P$ \4 x! W/ ]! H2 I
System Management Mode Core Interface Specification (SMM CIS) v0.91 (PDF 646KB) |
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