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Programming Interface for Bus Master IDE Controller Revision 1.0
# G8 I, Q u/ b- }1994/05/163 i; f6 h6 x! y6 o& j4 N
6 A1 f( s) k d, {8 P. rThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk$ Q9 j$ ~2 V4 @# W- I" a% W& s
controller that directly moves data between IDE devices and main memory. By performing the IDE data
6 {% E: I8 `4 P: g( w6 t# d r1 B/ Stransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)% R- n! t9 E$ h: u9 l: P' w
and improves system performance in multitasking environments.1 w9 G( S- |, F9 g$ `
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Until this specification is ratified, it is solely+ }6 H8 e7 Q- f! ~ V I" `& A
owned and maintained by:
& O, y# `6 x4 t7 e2 |( q4 }' ^Brad Hosler, Intel Corporation" R' `2 [- t& q4 Z
bwh@salem.intel.com (please comment using email)
0 E' [) D; P$ Y/ Q7 S: P503-696-8431 |
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