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Feature Summary" L9 {9 n+ s( @* {2 C4 n8 j
) X7 y8 Y( b6 t, r$ gLow Pin Count Host Interface (LPC) P; T! S6 |8 m& r% l
SIRQ supporting IRQ1, IRQ12, SCI+ W$ e% `9 [& k2 l! _/ b) x
I/O Address Decoding:
! ], q$ I: \+ a4 d0 v KBC IO Port 60h/64h
/ }2 N! K2 E1 e/ q8 M* | Programmable EC IO Port 62h/66h and 68h/6Ch$ [/ E( z0 f+ A% B! F- g4 ?
Programmable 4-byte Index I/O ports to access internal registers
s6 H0 l9 y d' } One Programmable I/O write byte-address decoding# K( X! [- X4 `& v. V9 w; f
" [6 X1 Q3 o5 k: O1 N8 E+ WX-Bus Interface (XBI)- T* V$ s+ h, r( |0 S4 m
SPI Flash support, the operation frequency runs at least 50MHz.
* a+ J: w) t/ X4 V Addressable Memory range up to 24MB.
/ F/ c& U. k( t. O) k7 X 8051 64KB code memory can be mapped into 4 independent 16KB pages.
; y7 B8 i% j! s; S R/ q! M7 S* K! P$ w
8051 Microprocessor+ U/ b$ c" _& r$ r
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.* g# n% `' Q9 V$ n" `
Programmable 8/16/32 MHz clock
* Y; F* y1 h/ C8 y7 K9 f, W Fast instruction fetching from XBI Interface% T) o. {# T4 `3 n& \7 Z
128 bytes and 2KB tightly-coupled SRAM/ ?% O, Y$ X% E, F1 w4 F
24 extended interrupt sources.$ O0 a _' e2 h& K
Two 16-bit tightly-coupled timer
0 B4 \' U4 O3 G2 b, |
- z. N* D! z6 N* I( K5 m8042 Keyboard Controller" W* I1 y( e6 O1 H
8 Standard keyboard commands processed by hardware) t$ D; M, Z$ H' P( W
Each hardware command can be optionally processed by firmware
" t4 Q t! g- g! w$ N# u. Z/ {# h' v0 x
Embedded Controller (EC)7 l3 a! p2 z# N5 b: ^
Five EC Standard Commands can be processed by hardware
: P$ {5 }+ d3 y! @3 _" n( ~ ACPI Specification 2.0 compliant4 y6 z8 h& o+ `7 f m4 o
Support customer command by firmware* I" k4 k. [6 {) T0 x D# G& W% [7 G
Programmable EC I/O port addressing (default 62h/66h)2 i; S! c! r: b- t# E; I
- J7 s- a( D4 g9 Y+ ^, ]
Analog To Digital Converter (ADC)0 v7 O* y( R, A1 }
6 built-in ADCs with 8-bit resolution.
9 ~7 l2 \6 j0 R* F4 n, U The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
: R0 i0 s# I, N# M: C, [
9 _% z9 k. T( R& P$ B* K, YPulse Width Modulator (PWM)( Z1 a1 o6 q0 m q; n/ J7 F
5 built-in PWMs; J' _1 L# l! r' s* r7 \
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.* W/ C1 |+ [4 g, h5 v
Configurable cycle time (up to 1 sec) and duty cycle.4 ]* x- x9 M; ]. {- t
" Q1 T1 |3 z' p) v4 Q; N8 |Watchdog Timer (WDT)
5 }+ s0 ]( S7 f6 @, b 32.768KHz input clock with 20-bit time scale.
7 v [( D( o. Y' Q4 ` 8-bit watchdog timer interrupt and reset setting
- W, @4 d1 |% k9 Q) E. d H6 ^: r) ~& ]
General Purpose Timer (GPT)" `* s& P2 g! G% @$ ]+ d) D& q
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution; d3 y" u# z, |: F s. Y
3 I3 Y6 S+ ]. u$ s8 @/ K
General Purpose Wake-Up (GPWU) d# H/ f6 o! \# S: u) S
All General Purpose Input pins can be configured to generate interrupts or wake-up event.
5 l2 c1 \6 x3 I" h% @
- X" N$ @6 c1 S) M# N2 ?General Purpose Input/Output (GPIO)2 @. Y( K& T. ^( F: X& m
All I/O pins are bi-direction and configurable
% h T. s- O( S! ?0 Q! h! y All outputs can be optionally tri-stated4 m6 f' O: \$ P2 A7 b
All inputs equipped with pull-up, high/low active, edge/level trigger selection7 Y0 p" ~' E0 }+ ]5 N5 J$ T
All GPIO pins are bi-direction, input and output.
3 X1 p/ {' Y# a Max. 43 GPIOs
8 q9 v2 D% O0 w6 {: K3 o( {
) ?) k2 P& C# W2 D1 V0 u. [Power Management
A, ?- w9 w4 L Sleep State: 8051 Program Counter (PC) stopped( Z v+ `" U; X2 E8 v
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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