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Feature Summary
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2 B& ?: I7 e. \8 e* nLow Pin Count Host Interface (LPC): D. j* m, `2 o$ z: }; M6 v; @
SIRQ supporting IRQ1, IRQ12, SCI
( S0 M( Z. ^. n+ A9 _% T! L$ R I/O Address Decoding:
7 p6 G: h+ A$ _" f KBC IO Port 60h/64h
: I3 y2 p1 {0 V* ]6 ^ Programmable EC IO Port 62h/66h and 68h/6Ch
# Z, o9 C: `" B1 M Programmable 4-byte Index I/O ports to access internal registers
7 A; Z x0 Z) D; M7 f One Programmable I/O write byte-address decoding
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( R5 z" N' }$ x) WX-Bus Interface (XBI)0 e$ q u m5 l; F! T
SPI Flash support, the operation frequency runs at least 50MHz.
1 S V. T8 h( W+ M1 A5 e* | Addressable Memory range up to 24MB.
8 z$ X h0 M [9 V3 Y* d! _# D 8051 64KB code memory can be mapped into 4 independent 16KB pages.
}5 E5 q+ V! W: f" n5 f% ]" n, B9 J4 q2 t, _( c: {4 J
8051 Microprocessor+ i- z& D5 H" h0 d
Industry 8051 Instruction set complaint with 3~5 cycles per instruction. g4 x* G* y& e
Programmable 8/16/32 MHz clock0 K, {/ G& ^8 h- ~+ n: \
Fast instruction fetching from XBI Interface
+ h8 ]9 o+ n: U 128 bytes and 2KB tightly-coupled SRAM
5 P. |+ |& e4 X6 }+ M 24 extended interrupt sources.; X% ], a& g2 V! [$ o. ?" X n& ?
Two 16-bit tightly-coupled timer! d- ~5 T; u7 c6 g
3 w0 J; p2 _: ~/ m# G/ q+ O
8042 Keyboard Controller: i4 d+ r; }9 q( z/ {, g
8 Standard keyboard commands processed by hardware# b1 S# m$ D2 o
Each hardware command can be optionally processed by firmware9 r# n; t" p D% |
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Embedded Controller (EC): `: s3 }5 n' b8 j0 J1 B
Five EC Standard Commands can be processed by hardware& e y* j! ?' W. y7 L7 c% \, S
ACPI Specification 2.0 compliant
% F9 ~+ x7 G' ~6 s/ D Support customer command by firmware0 q% ]. h& i+ V8 U6 j
Programmable EC I/O port addressing (default 62h/66h)+ R( t/ u q2 j/ k Q$ V/ p
6 u1 d6 T4 }' u/ V: I" n
Analog To Digital Converter (ADC)
7 {0 N$ h# R" }& X; k 6 built-in ADCs with 8-bit resolution.- z1 c7 ~% {' D6 S C! G
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).& H% k2 O+ {8 E M' N' \
6 q; r" g- ?$ G8 f3 T1 N& v1 OPulse Width Modulator (PWM)
% L2 z! p0 m6 M' H* J 5 built-in PWMs
8 i# e" _7 J. P/ G- m% B/ V Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
! ~8 [" k- Q' h Configurable cycle time (up to 1 sec) and duty cycle.
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Watchdog Timer (WDT)- e) Z! c8 C5 W5 ?7 S
32.768KHz input clock with 20-bit time scale.
7 ^/ y' N' A/ Q6 T7 J3 { 8-bit watchdog timer interrupt and reset setting6 T8 b5 p% Y+ L: m5 z
; I; Y# a& C0 s- v) F0 U- ~/ V( QGeneral Purpose Timer (GPT)
/ v' Y/ e8 T2 x. G" C# l$ N Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution: d# [) ~ H, A6 @: W
" \7 q4 m1 L L8 E2 V; |General Purpose Wake-Up (GPWU)
6 r- W- _! E* _$ R% ] R+ Q All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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- @9 K/ Y7 l7 kGeneral Purpose Input/Output (GPIO)
8 |; ]) P- C* l! d2 p% r2 p! I All I/O pins are bi-direction and configurable
. X8 a; \! A; U- e4 J All outputs can be optionally tri-stated
4 m' \5 u" J4 G F9 v; O All inputs equipped with pull-up, high/low active, edge/level trigger selection
. O% }" h( G9 m6 X0 V9 N All GPIO pins are bi-direction, input and output.8 t! ~4 w" J w6 y' y
Max. 43 GPIOs* \; @3 r" T# i6 U7 P* u! N
z1 k% C2 N3 H) L! r0 l2 W6 p) bPower Management9 ^ X0 ^ i, X$ A, B& b
Sleep State: 8051 Program Counter (PC) stopped) p' {3 Y1 R6 m- _) K* _3 w. n8 Z2 K
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.# M. d$ i+ ~( u4 W# D
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