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Feature Summary' m# ` t4 `% Q# [9 B
. d& ? ~% D* T) d0 y7 v; U$ ?Low Pin Count Host Interface (LPC)4 u& v" m' y$ {$ y0 N
SIRQ supporting IRQ1, IRQ12, SCI+ w0 c; S# O: ^
I/O Address Decoding:& V7 u% e/ p% N) ]" r4 q8 L4 F# R
KBC IO Port 60h/64h
! }) c) g. w( V1 Y Programmable EC IO Port 62h/66h and 68h/6Ch
! x0 I8 d3 h8 h B+ x* A* S Programmable 4-byte Index I/O ports to access internal registers
4 W% \8 f+ E% ]- x! U One Programmable I/O write byte-address decoding4 h& R4 K" p2 F) t" z
! u5 n/ w0 S. v, b; L5 LX-Bus Interface (XBI)
Q$ {2 [! `% K9 }5 s SPI Flash support, the operation frequency runs at least 50MHz.8 X" O) k1 q" X) U. n8 @" |
Addressable Memory range up to 24MB.
2 m( e C+ d; ^3 M 8051 64KB code memory can be mapped into 4 independent 16KB pages.
- {- R9 R+ I' u6 o5 _4 C& Y7 `& d
u% [+ b j" u. C8051 Microprocessor
$ L$ C! E! N% Q9 L U( P Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
9 R# O: W1 x9 i$ c2 _ Programmable 8/16/32 MHz clock
% J! K2 [ [0 Q5 Q7 ] Fast instruction fetching from XBI Interface
$ b% a' F5 [0 L; b5 X- Z! g- q 128 bytes and 2KB tightly-coupled SRAM
. W- l, ]$ J2 Q/ O$ f2 v 24 extended interrupt sources.6 Z( v& R3 ~& d6 L2 |
Two 16-bit tightly-coupled timer
/ y0 c, ~: v5 U- d+ u: o" z4 ]7 h, H( w+ O
8042 Keyboard Controller& s: P( L9 o$ S
8 Standard keyboard commands processed by hardware
4 `0 }3 m; B( Y+ v/ t& l4 c3 G Each hardware command can be optionally processed by firmware8 H A* [- s6 @3 [* n T6 `
! [, H" V( s- d, n* X" Z( h
Embedded Controller (EC)5 C6 z2 N7 `3 M
Five EC Standard Commands can be processed by hardware
6 D0 |6 y3 D7 l+ |4 w ACPI Specification 2.0 compliant+ Y) V5 X5 T Z6 ~2 j, N. Z7 N4 a
Support customer command by firmware, r# i& D$ C4 p9 W1 e, F
Programmable EC I/O port addressing (default 62h/66h)
5 h5 E6 s) |5 V5 A: E+ X* T; x, D! ?2 h8 M) J+ I" n
Analog To Digital Converter (ADC)4 Y% G4 L# v$ j
6 built-in ADCs with 8-bit resolution.5 r6 ~4 i# g% X# t
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
1 ^( v8 |, v* ^5 K3 {6 h" D
, @% |0 K4 ~0 @# b. @* J$ WPulse Width Modulator (PWM)& q. A% t9 l, p# {2 O1 d
5 built-in PWMs
8 J; S0 H) k. A5 ?! ^& w Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.0 [/ p' u4 B* N. \* I3 R
Configurable cycle time (up to 1 sec) and duty cycle.
, d: S! H" \" U) G" y# a: D) d: O9 a8 m* R1 B7 j: H1 c: z
Watchdog Timer (WDT)* @: n& X; \3 J+ y% c9 H
32.768KHz input clock with 20-bit time scale.
7 a! }& z' H$ d4 [, k* U 8-bit watchdog timer interrupt and reset setting$ ?6 B* s0 ?+ ?6 a5 u
: ]9 i, j; z+ c
General Purpose Timer (GPT)
, L6 h" J1 g; q0 _ Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
9 o! a: L( G! |! \+ a8 v0 [& }. f5 y/ Z- m( D' W5 S
General Purpose Wake-Up (GPWU)
- N7 u) B3 c% |) v( f All General Purpose Input pins can be configured to generate interrupts or wake-up event.
' S3 j+ j) b0 ^) U- a6 m% F& j5 p; [( i
General Purpose Input/Output (GPIO)
! }, {3 A8 N1 q All I/O pins are bi-direction and configurable! V) o: R0 J" }
All outputs can be optionally tri-stated
5 t; ]1 _/ u2 ~ Z( O' \/ ?4 u8 z All inputs equipped with pull-up, high/low active, edge/level trigger selection. ^+ X6 s3 Z6 \
All GPIO pins are bi-direction, input and output.
, m; U F5 e; q0 |5 U& ~/ y Max. 43 GPIOs( S& N8 g, [+ f+ x1 P- Y4 H
$ m2 c, `7 H) w2 d2 U. ZPower Management" P c# b- p* p& b3 x& i
Sleep State: 8051 Program Counter (PC) stopped1 \+ |, _( C' c' r0 X5 ?( H
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
2 f' M: F+ v/ H B/ `! [) ?6 o8 e" f3 F
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