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Feature Summary' T% v# P5 u3 K
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Low Pin Count Host Interface (LPC)( u8 V: B% O# m& n# p- A1 N
SIRQ supporting IRQ1, IRQ12, SCI
( V( y* K! f' P0 g6 e I/O Address Decoding:- t( G7 |/ D& [4 |# S
KBC IO Port 60h/64h
1 C1 T, Y+ S+ I6 a& {) j Programmable EC IO Port 62h/66h and 68h/6Ch
% m3 k4 y3 h F' h Programmable 4-byte Index I/O ports to access internal registers
( G: D) X9 g4 W- A/ ?# ~ R% b o One Programmable I/O write byte-address decoding( x# e% L5 \. H# }% r2 z0 {
( J: I' T9 {5 iX-Bus Interface (XBI)
2 i$ J9 l# F$ t1 ]% C6 f5 O4 P @ SPI Flash support, the operation frequency runs at least 50MHz.+ z* l7 b/ G- J8 x0 A' g; O$ ^* D
Addressable Memory range up to 24MB.) d1 k- X+ u+ P6 k9 q& E/ X+ C
8051 64KB code memory can be mapped into 4 independent 16KB pages.
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8051 Microprocessor* h* d% `# J* \$ ]0 ]. q
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.7 A2 C* v) h) m/ W9 @2 F# B d
Programmable 8/16/32 MHz clock
! D' Z$ N' V+ Y" v' A Fast instruction fetching from XBI Interface: M% x9 X1 X! o4 @& y
128 bytes and 2KB tightly-coupled SRAM8 v5 d" K$ [8 f, U
24 extended interrupt sources.
~/ ?' ~& ?6 L+ j. [7 f1 m% D Two 16-bit tightly-coupled timer
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8042 Keyboard Controller) H! J2 B( r5 A z7 G+ t
8 Standard keyboard commands processed by hardware5 E! {5 ^9 s1 m
Each hardware command can be optionally processed by firmware7 e+ T; K6 c! g* m2 m* q
9 A$ d: p" q* n% c- tEmbedded Controller (EC)
. L; O- C( K4 q6 T Five EC Standard Commands can be processed by hardware
7 {& l/ t# A1 H3 n8 ^: c ACPI Specification 2.0 compliant6 \! v+ O/ F% u
Support customer command by firmware
/ |; S, [6 [8 S8 v Programmable EC I/O port addressing (default 62h/66h)7 N2 u' ~) g: v9 l/ C+ T
7 D' ~( B4 [$ G. o& u7 g
Analog To Digital Converter (ADC)$ n1 {( a* C/ m9 a
6 built-in ADCs with 8-bit resolution.
; ?7 n z5 [. k1 y The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
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- w9 M$ ^- {% T- a$ p. BPulse Width Modulator (PWM)
' b+ [! g6 A( M4 b, Y0 v- y# J/ | 5 built-in PWMs
& X( Y+ C) a% X2 Y Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
" r' P& V. G) F) Z Configurable cycle time (up to 1 sec) and duty cycle.
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% F2 _' {- f, CWatchdog Timer (WDT)" ~8 R" Z1 e: H5 Y% g* d0 G
32.768KHz input clock with 20-bit time scale.
* |/ ]. a1 I( n$ [, a 8-bit watchdog timer interrupt and reset setting
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General Purpose Timer (GPT)7 S; s6 z$ M" ]7 p' x, X% K
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
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* I2 p. t* o7 YGeneral Purpose Wake-Up (GPWU)3 z$ H! |8 d8 N7 V
All General Purpose Input pins can be configured to generate interrupts or wake-up event.3 t$ @( |$ b4 W" ]
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General Purpose Input/Output (GPIO)) Q# t# w7 c: F$ V2 k: T6 I) z
All I/O pins are bi-direction and configurable: y$ }* g9 R* z0 y- U8 E% _
All outputs can be optionally tri-stated
6 y4 T2 Z% `: v5 |% V6 B$ ~ All inputs equipped with pull-up, high/low active, edge/level trigger selection- j0 j" Q: d: y0 B/ Z( S
All GPIO pins are bi-direction, input and output.! q9 ~; {9 ~4 E! Y9 ]
Max. 43 GPIOs: I5 D& r4 {! l6 [! t/ K8 W3 g
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Power Management
$ H6 P9 J# G* f3 ? Sleep State: 8051 Program Counter (PC) stopped
6 R, @7 s7 i+ x! i5 G) [# T# L Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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