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Feature Summary* O6 i! ^$ D5 C7 \! V: M
5 [9 O- y4 N$ U5 M' P8 sLow Pin Count Host Interface (LPC)4 N4 K0 |. A c# ]* g. M9 t
SIRQ supporting IRQ1, IRQ12, SCI. C/ z0 Y, ?/ o& P6 ]# Y1 e+ W+ j1 ^ s
I/O Address Decoding:. D& x8 V( H! g" {5 K
KBC IO Port 60h/64h, h4 S- I [7 |2 h |7 j
Programmable EC IO Port 62h/66h and 68h/6Ch
3 ?, z( R* X7 h m3 c Programmable 4-byte Index I/O ports to access internal registers
t4 u5 j4 j- ] g% c- Y: t One Programmable I/O write byte-address decoding
8 x* @: N. I0 J4 K
" y7 B% {5 a' S; hX-Bus Interface (XBI)$ m2 _7 D' ]$ b5 a1 b4 N# U7 ~
SPI Flash support, the operation frequency runs at least 50MHz., A4 }% r( `0 X5 F
Addressable Memory range up to 24MB.! ]5 E% Q' X: X' u
8051 64KB code memory can be mapped into 4 independent 16KB pages.
9 p% H, V; `1 B5 t2 A- w+ ^. q/ J5 b1 q( }* W, S$ n& X
8051 Microprocessor
- ?- S$ O' i: X, O Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
0 u. I: c5 K* w# h0 C5 Y! w6 L Programmable 8/16/32 MHz clock
: m$ k7 ]) D2 J4 e$ ?6 l Fast instruction fetching from XBI Interface3 E/ p8 N* V; }
128 bytes and 2KB tightly-coupled SRAM" V6 }7 L z7 u, n: z' h
24 extended interrupt sources.
5 p4 F# [* j# U. _+ ~/ E# q Two 16-bit tightly-coupled timer' ~! V! C" U# x# D9 v
+ I8 r: D: x/ S
8042 Keyboard Controller
% A/ l4 y: t$ k 8 Standard keyboard commands processed by hardware
3 A( j& }5 l) C$ u Each hardware command can be optionally processed by firmware
1 L1 b$ F) G1 h" g9 m1 P5 }5 h7 R2 B! i% P
Embedded Controller (EC)/ T0 j& \9 `) r4 N' j1 G
Five EC Standard Commands can be processed by hardware; {" C& K! l8 p( J9 {
ACPI Specification 2.0 compliant' }* v+ ~% B. k; H
Support customer command by firmware- ^1 U1 e$ N; c9 B2 z
Programmable EC I/O port addressing (default 62h/66h)
, d% c+ p0 o! c: m* W2 t/ Q# C" N( Q" J1 P
Analog To Digital Converter (ADC)
4 Z* l0 C7 b( {5 \5 }8 D) T 6 built-in ADCs with 8-bit resolution.
* k( C$ R# J* g6 s; R The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
. o+ M. k2 l9 e* s3 K+ L( g5 E$ q2 B) F" \& N! B
Pulse Width Modulator (PWM)
- v' P9 D) W' e! q0 K/ B 5 built-in PWMs
% F* q8 ]9 W" m Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.1 ]) D; z6 L, O, b' G3 P
Configurable cycle time (up to 1 sec) and duty cycle.$ _! c- {8 b, T1 ^! H
6 \& T! f+ m: k$ y0 y
Watchdog Timer (WDT)3 Z. H }" ^9 Z; G- e# j; |1 D+ O
32.768KHz input clock with 20-bit time scale.: J4 e) Q. n" w
8-bit watchdog timer interrupt and reset setting; _1 n$ M$ u5 A5 k( e- x
! }4 _9 I8 }. ]5 qGeneral Purpose Timer (GPT)% d6 n# K# @3 z, j
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
) @/ v+ U! [1 \) E' h4 Q, ?; D* [9 r0 l! b
General Purpose Wake-Up (GPWU)$ ]/ {0 f% Y: e* Q
All General Purpose Input pins can be configured to generate interrupts or wake-up event.
p. f% C) Q. P+ u3 J2 @
9 |. B7 g. I, X g5 Y8 t- F: ZGeneral Purpose Input/Output (GPIO)
6 k! _, p) O. f) ~4 W All I/O pins are bi-direction and configurable7 R% J0 j6 Y$ H
All outputs can be optionally tri-stated
! k& c6 h8 q% r( K: U All inputs equipped with pull-up, high/low active, edge/level trigger selection
$ F( G- X! j% p3 B' s All GPIO pins are bi-direction, input and output.
( j, K0 F( U, `# R3 T Max. 43 GPIOs- G+ G5 @! w _1 M; h) v* c5 p1 D
2 ? A' b8 ]7 r/ t, h: y4 ?: J
Power Management6 x& d- v9 Q! a, e: u
Sleep State: 8051 Program Counter (PC) stopped% ]4 y6 I: K9 ^8 j+ V# O% w
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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0 E2 D! z& G9 |5 B8 mTotal Pages: 40 |
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