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Feature Summary& @. b% X7 {5 G1 x3 ~
' `, r4 S& U6 d# r; }Low Pin Count Host Interface (LPC)8 y3 y" ]- h" G
SIRQ supporting IRQ1, IRQ12, SCI
+ l; d( R* ]" T9 l# s; w/ U I/O Address Decoding:
7 |# R5 ?; k' R KBC IO Port 60h/64h
$ P9 T7 ]) M; ^& o& `: s l; b& C T Programmable EC IO Port 62h/66h and 68h/6Ch
/ q0 _$ b. R3 T. d! Y Programmable 4-byte Index I/O ports to access internal registers
: e3 f& v$ A9 T One Programmable I/O write byte-address decoding
. a+ `: S: [: k4 P( V; }2 `2 R
! |* x7 P8 k" ~/ [: F8 _" wX-Bus Interface (XBI)
# t) G/ [6 m8 l. C SPI Flash support, the operation frequency runs at least 50MHz.
/ P; H1 r2 n. z, A8 Z6 V( W Addressable Memory range up to 24MB.* ?+ U% W0 j6 E7 f
8051 64KB code memory can be mapped into 4 independent 16KB pages.* u$ v5 e3 t9 C9 p8 h5 _
. A4 J: f) w0 h% z; V
8051 Microprocessor
0 o c* w+ R6 E2 I$ T Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
/ [1 B! C' M- s5 @ Programmable 8/16/32 MHz clock
. W# Y: K1 ~3 j, ` Fast instruction fetching from XBI Interface
( O4 l' n' N; p 128 bytes and 2KB tightly-coupled SRAM% l4 H% M1 D. c/ P
24 extended interrupt sources.% v9 Q& \) V' l: A! c
Two 16-bit tightly-coupled timer
4 ~1 k# b8 e4 W2 \
) s1 s. R7 c, P# K8042 Keyboard Controller
1 j9 }5 y6 A s( | 8 Standard keyboard commands processed by hardware$ v2 ?6 R# @% T6 K# F7 t! q
Each hardware command can be optionally processed by firmware" p1 ~! l' O+ v0 t' H- l
7 W/ K. d2 z& F9 `- h
Embedded Controller (EC)# w8 A4 K7 |5 s
Five EC Standard Commands can be processed by hardware
- M2 b8 I/ o2 g ACPI Specification 2.0 compliant+ M0 v4 a$ N) O) h a
Support customer command by firmware
+ x4 N ^$ \. a Programmable EC I/O port addressing (default 62h/66h)
( ]3 ^% l! o( Q7 X/ s1 d! g0 M
: P7 f( k/ S/ p! J _5 KAnalog To Digital Converter (ADC)
; v- k. o( x* q+ A4 g 6 built-in ADCs with 8-bit resolution.
- e& I! g% r" [: H; U The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
+ B/ D) F9 g# y9 y& w2 a
) C! d/ ^( G6 Y, J1 Z% I" B! _Pulse Width Modulator (PWM)- [0 h- m5 S! F# S' E/ v4 Z: s
5 built-in PWMs
6 |: y# A, o! R R" E) s2 U7 l Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.1 \) h" s9 O' Q$ e
Configurable cycle time (up to 1 sec) and duty cycle.7 E0 _6 W* k3 J4 ^% |
) L8 p+ H8 `' ~$ BWatchdog Timer (WDT)' H$ [) I* [2 M' J9 j
32.768KHz input clock with 20-bit time scale.5 y! b" h- G0 C0 b
8-bit watchdog timer interrupt and reset setting
+ L3 c8 u9 v) c$ m" p1 E3 R4 Q. s" ]$ L) L
General Purpose Timer (GPT)( M5 P* t3 Z4 e' Q+ j: c) M, x0 A
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution# R( P8 E+ _! M* X1 A
$ ^7 L& \8 ]% Z- F1 m
General Purpose Wake-Up (GPWU)
/ Y l- r! g* D All General Purpose Input pins can be configured to generate interrupts or wake-up event.( k' ~4 K. y0 v: ]* G. ~ K
& u- r/ @8 x+ k; T' K
General Purpose Input/Output (GPIO)' \1 A/ I3 _2 G' J) U# e! j
All I/O pins are bi-direction and configurable
$ Z6 k7 B( i, p6 ^5 ?; K All outputs can be optionally tri-stated) F9 r# D$ k4 i9 z' W- } N
All inputs equipped with pull-up, high/low active, edge/level trigger selection3 E$ a) }0 ^# {2 N/ Q- @% |/ M
All GPIO pins are bi-direction, input and output. N/ ^! i5 y4 Y' ]* b3 y* I3 a' D
Max. 43 GPIOs; ~5 t7 l3 j! p* w. y" J1 U% V
# w j4 a5 O; B- a
Power Management
* i6 m6 B; R+ l Sleep State: 8051 Program Counter (PC) stopped& P6 s& J+ H$ n0 k" [8 g" s5 p
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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! _# l; S- j4 o Y* `8 ~% H* \& cTotal Pages: 40 |
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