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Feature Summary
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, b- Y }& l W/ C! s7 K: X' D HLow Pin Count Host Interface (LPC)2 ?1 U# j( F: Q; K
SIRQ supporting IRQ1, IRQ12, SCI( m L- ~2 a, k' s$ x8 r1 y% o
I/O Address Decoding:* o, q+ p4 ^6 x' U
KBC IO Port 60h/64h
5 t# v$ Y# B% h( [! p0 l& D( E Programmable EC IO Port 62h/66h and 68h/6Ch- V, a! l! M/ d; o0 o+ w
Programmable 4-byte Index I/O ports to access internal registers% x+ @" `6 y/ l+ c% \
One Programmable I/O write byte-address decoding5 x; J, y m' R9 ~8 h# k" i
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X-Bus Interface (XBI)) k) j4 f2 x( G6 K# B0 f7 P! t
SPI Flash support, the operation frequency runs at least 50MHz.
5 g' i3 [# @: m1 X- Q Addressable Memory range up to 24MB.
% R" \. N, s5 H7 x 8051 64KB code memory can be mapped into 4 independent 16KB pages.
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1 |. ~1 P2 b& n+ l0 x( V! s8051 Microprocessor: H; a! ?" j0 O. C8 }2 L
Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
! _/ M: k2 w% ~( h5 Q Programmable 8/16/32 MHz clock
9 K) T1 D' N) ?/ { J. \ Fast instruction fetching from XBI Interface
$ | r& ~1 N8 \( @* ` 128 bytes and 2KB tightly-coupled SRAM
' ?( g6 ~: Q& S. T 24 extended interrupt sources.$ t$ d& W& R% `7 H
Two 16-bit tightly-coupled timer
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9 @) E5 h+ x% N3 y# f8 q% b+ E, ]8042 Keyboard Controller
! m9 W- Z) W3 {8 w0 f* T# [ 8 Standard keyboard commands processed by hardware$ ^0 R& m+ C( v0 u
Each hardware command can be optionally processed by firmware- n# p5 b& F% `/ p; p: q& c1 G
# ?% U' |. x! M5 M- HEmbedded Controller (EC)! z1 u n' w) s0 ?/ b R# m
Five EC Standard Commands can be processed by hardware
' k( U: c& |3 v$ i8 X5 Q ACPI Specification 2.0 compliant* }- f0 K+ f- x) v$ J' t# x
Support customer command by firmware4 K0 Z$ n2 @, k) E- G& ~8 Q
Programmable EC I/O port addressing (default 62h/66h)5 z- _$ S4 c- ~) t* l- f3 @* @' S
- D% r( j- g1 r2 Q% \0 JAnalog To Digital Converter (ADC)
( y5 [ Q$ G+ ]& E5 P 6 built-in ADCs with 8-bit resolution." ]: B. ~% O+ j8 u' _
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).7 @% n. [8 \' L$ u. K
) _: T+ U% q$ O) m& [Pulse Width Modulator (PWM)
! c' d0 N8 B: h! m' i+ I$ m% J 5 built-in PWMs
0 D9 C3 A2 _& W; T+ Y: l5 j6 ^ Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
^+ z( O4 i( ^; j5 v1 x" `( [ Configurable cycle time (up to 1 sec) and duty cycle.6 v# b) |5 f5 I q7 G" C0 l
% g9 [) y* t/ {+ ]1 ~* D- h( p oWatchdog Timer (WDT)
8 S2 j H' ~5 ^+ d( y 32.768KHz input clock with 20-bit time scale.* ~7 k* m! K- x& H- p
8-bit watchdog timer interrupt and reset setting" q Y, Q% f# n0 P. s8 @8 K+ Q9 Q% z
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General Purpose Timer (GPT)
4 ]5 G$ m3 I9 e' ?4 V$ c8 f9 l2 L Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution) N1 C# j: N) |6 [, }, |
! ?, J9 r$ B) m n/ S6 S3 DGeneral Purpose Wake-Up (GPWU)6 q g1 [0 [/ L- X g" i( |$ ~
All General Purpose Input pins can be configured to generate interrupts or wake-up event.7 d3 ^: V+ i0 i) ]/ @4 [% n6 ~
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General Purpose Input/Output (GPIO)* C$ z$ L4 E+ R; e+ ]9 W: {7 R7 W
All I/O pins are bi-direction and configurable
3 e0 i& A: Y7 ^$ `/ W All outputs can be optionally tri-stated' f/ {$ f- _/ n$ ]
All inputs equipped with pull-up, high/low active, edge/level trigger selection
% g( t& ?. V. g, K+ G( G, I All GPIO pins are bi-direction, input and output.4 d8 t9 E9 m! h$ l; h& Y& c
Max. 43 GPIOs
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Power Management' d' a% g4 k5 S% \0 G0 {' s( L
Sleep State: 8051 Program Counter (PC) stopped
5 i- z! h' ?& C* M, M) s5 T Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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