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Feature Summary% E" H) f' `% A+ Q: l e0 o" e
7 N' E5 L% I" P* B9 \+ Z
Low Pin Count Host Interface (LPC)/ ?, K, @6 O* L. W# u# r! G6 c9 q
SIRQ supporting IRQ1, IRQ12, SCI
0 A0 f7 b: ~' G% p* R2 i I/O Address Decoding:" w) w* \; O9 C5 T) d/ n- _
KBC IO Port 60h/64h
# G& h5 U* G# }, u( G0 g Programmable EC IO Port 62h/66h and 68h/6Ch! i6 l% x, i4 @/ {; `; V" }
Programmable 4-byte Index I/O ports to access internal registers
+ i( |! x0 [6 n: D# P& w One Programmable I/O write byte-address decoding$ M/ l" C* z1 v4 _; C+ T. {
* }' ?4 K! E' [0 i; o1 OX-Bus Interface (XBI)& B0 S) @6 |' m M# `% w( ^
SPI Flash support, the operation frequency runs at least 50MHz.8 d3 e+ A1 a( W
Addressable Memory range up to 24MB.
/ K2 w, F$ }5 Y; K3 g8 @ 8051 64KB code memory can be mapped into 4 independent 16KB pages.
0 y& D( X2 {/ g$ a9 w% c. Z+ j' p M
8051 Microprocessor
+ F: ]( |! n9 y) j; J9 q* h Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
7 p2 g0 [8 T# c ]/ U Programmable 8/16/32 MHz clock$ w7 d: Q' s$ T6 r' L
Fast instruction fetching from XBI Interface
* x# J. e0 G9 \, @8 q( h 128 bytes and 2KB tightly-coupled SRAM" K% Z5 i0 w( f9 s: { h
24 extended interrupt sources.
. J* C$ ?, t1 l& K* p, j' S5 ~: P _ Two 16-bit tightly-coupled timer. n7 P+ h- @) i) Q- j' @" u, W
7 a/ J4 R* {3 @3 a# i3 ^
8042 Keyboard Controller
/ V0 V, z* D6 K8 [+ N8 u; ] 8 Standard keyboard commands processed by hardware
- O" Z: ~/ H# Q/ \& E Each hardware command can be optionally processed by firmware
5 ~9 x. f s( M d1 ^0 g3 c* M1 T
v& W, E* T6 v7 NEmbedded Controller (EC)
6 q9 e% D K, p: J8 e Five EC Standard Commands can be processed by hardware+ h2 ]+ J9 |$ @: ]$ [5 `
ACPI Specification 2.0 compliant/ E+ T/ m! g. z. m
Support customer command by firmware2 T0 O; S9 {& a, d( @- R4 T6 a
Programmable EC I/O port addressing (default 62h/66h)* z8 Z2 Z+ W8 M
1 U) m$ _. [! l8 {( B. \
Analog To Digital Converter (ADC)
9 T6 y/ f" x i7 @: X) e 6 built-in ADCs with 8-bit resolution./ w. C# i' Q; I" c2 }9 P
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).0 s; o8 W( \ P) I+ u( L4 @+ W
% d# J! g- n. P8 U5 |% `$ \6 X
Pulse Width Modulator (PWM)$ C8 g X* g; b2 u( ~1 n$ y* y
5 built-in PWMs
2 I5 x: F5 H1 c2 o6 Y Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
" b0 `, o" L* u( g9 F/ B( S Configurable cycle time (up to 1 sec) and duty cycle.
- h3 n7 D, g s& e2 ?2 E' z- L( ?4 N+ n2 b2 n
Watchdog Timer (WDT)5 o0 C/ A6 `1 l! L2 X1 }4 s
32.768KHz input clock with 20-bit time scale.5 L9 ]( M+ D) O6 L
8-bit watchdog timer interrupt and reset setting; [+ F; ]- Z+ z8 ?5 i
3 N& L, h5 K7 m
General Purpose Timer (GPT)& e' z: [& A1 A% _6 `, u
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
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% O. W- m. I; ~General Purpose Wake-Up (GPWU)
~6 s$ ]8 R+ z( q. z- L All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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General Purpose Input/Output (GPIO): Q+ M' j$ j" G |! v& T, ?' ?$ p" N
All I/O pins are bi-direction and configurable
4 f7 t+ R! Z1 J All outputs can be optionally tri-stated
3 ?/ r* w5 P0 A" k0 _$ u* \ All inputs equipped with pull-up, high/low active, edge/level trigger selection
, w% P6 R3 a( }. J0 M' e9 t4 m All GPIO pins are bi-direction, input and output.. s- }9 N: Z- V6 {
Max. 43 GPIOs j0 P( U1 Q2 d9 b7 W) G5 g7 A3 Q
# \1 N9 N5 f% d! T5 \8 h. @Power Management; e V0 H$ P5 H) a
Sleep State: 8051 Program Counter (PC) stopped) Y9 v2 e" a8 \9 Y0 r
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.$ z" u, c% I. x3 U9 a- X
+ Z2 J5 q1 E% t( t; ?) dTotal Pages: 40 |
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