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Feature Summary( s# z" U+ u4 Y" z( Q3 C$ D$ Y
" f: ^3 T; @% D: \: z8 R: ]3 _Low Pin Count Host Interface (LPC)
% g- u k z2 {" p/ c SIRQ supporting IRQ1, IRQ12, SCI
6 K" E4 N/ |1 C# E I/O Address Decoding:( j; d" | P4 f" I! i: ~
KBC IO Port 60h/64h- o% e% ]9 e# \5 F+ i$ Q+ z$ L7 ~
Programmable EC IO Port 62h/66h and 68h/6Ch: i1 u5 g) Q8 z6 N y5 j3 M
Programmable 4-byte Index I/O ports to access internal registers
6 p! {/ t- t8 D9 Q2 Z' V, Y& ? One Programmable I/O write byte-address decoding; i6 S" Q4 e( f6 @
1 v! i! H' f; r4 s+ x/ J; Z
X-Bus Interface (XBI)9 @1 Z2 i8 ?1 r& Z: @( D
SPI Flash support, the operation frequency runs at least 50MHz." X+ W O3 E' L. |" g6 [' z8 _
Addressable Memory range up to 24MB.
/ p4 S7 T, g* P; ^6 O- d 8051 64KB code memory can be mapped into 4 independent 16KB pages. O# c* g6 w& y8 e3 r& V# Q! r
5 x' T+ Q* X0 D9 o4 o
8051 Microprocessor
' e- z) P* x! f- T& z6 a: s Industry 8051 Instruction set complaint with 3~5 cycles per instruction.4 c, @ w( c. a5 K' }& s
Programmable 8/16/32 MHz clock5 g6 R% ^* W8 g% r0 L5 V
Fast instruction fetching from XBI Interface P, m3 c- Y) X/ e( k
128 bytes and 2KB tightly-coupled SRAM, }) ?$ u# Z- ~7 y
24 extended interrupt sources.6 |: ]8 d ]0 @1 [. V+ t
Two 16-bit tightly-coupled timer
: y# F# t r `
! Y: \. C- y, Z7 K/ v8042 Keyboard Controller. _' O0 y* R5 J6 J$ ^# ?% J. U
8 Standard keyboard commands processed by hardware
3 H4 x; S% {: a2 T3 d) c: R) H6 z Each hardware command can be optionally processed by firmware; C4 Y2 r) z; R8 W/ K4 z
4 U1 j7 M4 C5 a6 \! a
Embedded Controller (EC)% V$ m* Q! I7 X3 R0 J
Five EC Standard Commands can be processed by hardware+ D6 {6 H; c ~
ACPI Specification 2.0 compliant
; J' g+ c1 ^2 y5 w Support customer command by firmware
0 u2 Y- y% S1 b/ \! H/ H/ O7 k Programmable EC I/O port addressing (default 62h/66h). M4 Q' M" t) e- U8 C, |" C0 D/ v N
1 a6 J! d T: O, K' P3 ^ j: FAnalog To Digital Converter (ADC)9 n G8 ]8 l; `
6 built-in ADCs with 8-bit resolution.
1 d6 p! _4 z# i' l" I/ [' h The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
0 Y0 Y( @' q ^$ @) U1 V7 u1 f
8 r* r! F. J% P* T/ m$ VPulse Width Modulator (PWM)+ s0 J) Q. |8 i8 V' ]- u
5 built-in PWMs' @9 ?) u9 I. n5 B$ {
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz. D: G4 x2 x5 D; f
Configurable cycle time (up to 1 sec) and duty cycle.1 `- Z3 O! c1 J6 ?
7 x- O% X$ k4 N7 o: ~: w
Watchdog Timer (WDT)4 k3 n9 m0 ^/ L }
32.768KHz input clock with 20-bit time scale.6 K" r! t; Q1 b
8-bit watchdog timer interrupt and reset setting
1 Q) e5 o+ S& {- C/ E9 x
) ^8 e9 x- \5 A- hGeneral Purpose Timer (GPT)! i1 m& X" {2 N/ m& Z7 Y- v! F
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution9 F4 ?* R( d/ z- W8 B0 a/ }0 E
& N( i( w" `9 {% o* C
General Purpose Wake-Up (GPWU)) {% f7 u" g7 n7 l2 r0 x
All General Purpose Input pins can be configured to generate interrupts or wake-up event.
6 K8 z! e! ?, ? [0 N# B* e8 G- G" U$ h; N+ _1 ?+ Z2 C/ A) c
General Purpose Input/Output (GPIO)
; c; e: k8 C! p9 D5 {: h1 Q0 g All I/O pins are bi-direction and configurable
% G0 o$ d3 c( } All outputs can be optionally tri-stated2 y3 b' g4 n2 b( L
All inputs equipped with pull-up, high/low active, edge/level trigger selection5 P$ f. ^8 o+ l% U1 E+ s
All GPIO pins are bi-direction, input and output.) ]/ a8 [2 _7 P( r1 k; q+ P& e
Max. 43 GPIOs
' w% f" G7 |, H* p$ i
3 T. x( J$ [/ t; N* L- I+ lPower Management
) F6 {0 v, r8 @ w Sleep State: 8051 Program Counter (PC) stopped( h1 p& |/ Z& f8 t; g+ I
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
# `/ f" z8 C. m) r9 ?' h! y: z. V) N& t0 v" p
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