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Feature Summary# U7 r! K# S+ F9 X% s& b8 K* l& a/ d
+ N: W" d% ]8 v( uLow Pin Count Host Interface (LPC)
( {0 D0 B0 ^; E% r# I' \ SIRQ supporting IRQ1, IRQ12, SCI& t. K9 g5 s |
I/O Address Decoding:: S ]5 k9 K5 Q J
KBC IO Port 60h/64h
- T; |! | n1 D. i |. M Programmable EC IO Port 62h/66h and 68h/6Ch% v+ i4 C! T' t8 @* K' n% w0 W: s3 l
Programmable 4-byte Index I/O ports to access internal registers
8 {% i; T$ a# G8 [8 h One Programmable I/O write byte-address decoding
# e5 ?8 U' y& V1 z" M2 e
/ [( j0 g* N( ^1 `2 iX-Bus Interface (XBI)' B( ^. ?+ u$ a6 }/ Q/ u
SPI Flash support, the operation frequency runs at least 50MHz.5 ]$ K X0 K" K1 }, v
Addressable Memory range up to 24MB.
" }# ^- N7 v# A* d3 @; W; y8 U 8051 64KB code memory can be mapped into 4 independent 16KB pages.- ^% S2 ^" B O
- s- K0 v- B+ X. V% y* V1 M+ s' x
8051 Microprocessor
/ v7 d8 y5 G4 M* V) w3 A Industry 8051 Instruction set complaint with 3~5 cycles per instruction.6 V7 B7 z9 |( ]- H
Programmable 8/16/32 MHz clock
3 f( a( L% p, s9 j. w2 e$ P Fast instruction fetching from XBI Interface# s- Y4 R& V6 C1 \3 ]. g
128 bytes and 2KB tightly-coupled SRAM. [/ { V+ S1 I4 A; c
24 extended interrupt sources.: P) s9 {; a4 f! p) Y0 F
Two 16-bit tightly-coupled timer. G3 \% y8 |3 C9 [
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8042 Keyboard Controller+ E5 |! A( b7 o1 c
8 Standard keyboard commands processed by hardware8 W0 z% }& d) ~+ E; E
Each hardware command can be optionally processed by firmware3 w! @. X2 E" P) z, q& z: d2 |/ T/ ~
8 m# d4 G. y* |3 B9 R
Embedded Controller (EC)- U7 r% V* M- R( c
Five EC Standard Commands can be processed by hardware
& T" ~, n% W4 S ACPI Specification 2.0 compliant
e; ~: L9 d/ f% h, \ Support customer command by firmware* T) r# Q* j, H2 S# s% L( r
Programmable EC I/O port addressing (default 62h/66h)3 U/ |+ l+ G1 i, {- D+ }
$ w# s( \4 B! q% ?
Analog To Digital Converter (ADC)$ T" F4 v5 [: D. M9 R9 x) s
6 built-in ADCs with 8-bit resolution.
( H& z" a s! H" z5 S0 ` The ADC pins can be alternatively configured as General Purpose Inputs (GPI).: K5 H6 h) _6 q' n E+ r
! i$ e1 S# }9 cPulse Width Modulator (PWM)
6 i0 Y0 s# I& z5 X1 s" {8 { 5 built-in PWMs
7 j2 q: T: T- u Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
& g2 t. i* a$ | Configurable cycle time (up to 1 sec) and duty cycle.
2 o- q0 Z" P) I4 g- b7 }" H5 O. z- ^; y0 B% \
Watchdog Timer (WDT)* y7 P1 t9 c+ T0 V
32.768KHz input clock with 20-bit time scale.% X4 B9 P$ y' ~( U4 g+ j/ |, n
8-bit watchdog timer interrupt and reset setting5 {' ^3 N9 @# v+ H
0 Y% B/ T& p8 O% Z4 \8 M( H
General Purpose Timer (GPT)
0 j6 F7 j4 V. Y4 \: f Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution, B5 V3 m' F3 Q. A* b6 O" V+ {
4 f, S- V% u/ l, X4 R
General Purpose Wake-Up (GPWU)
0 H' q, ]; Z. h: n X2 A- I4 C All General Purpose Input pins can be configured to generate interrupts or wake-up event.% n1 d5 u( i% K4 f
8 F6 R+ t( J. q g% v$ \5 ^- X
General Purpose Input/Output (GPIO)
# w9 k( V8 v) M7 P7 C All I/O pins are bi-direction and configurable
" b: q! B8 Y% P All outputs can be optionally tri-stated
, v% }# N, J% r9 y% ?# j All inputs equipped with pull-up, high/low active, edge/level trigger selection
7 ]/ {1 O3 H3 o6 r) e1 W All GPIO pins are bi-direction, input and output.( p: s# Y, i5 [5 C* ^- Y) N
Max. 43 GPIOs1 o" \" m2 ]2 R- Q% V I3 B
2 l; T- r- K# H$ J8 V$ APower Management0 g1 ?! A! I- B: t" v1 @1 X
Sleep State: 8051 Program Counter (PC) stopped. \& _5 c' w- k6 y( L$ e
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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! Q& U8 c8 }1 ~( [Total Pages: 40 |
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