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ENE KB3700 Keyboard Controller Datasheet R0.1 2006

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发表于 2007-12-21 18:08:39 | 显示全部楼层 |阅读模式
Feature Summary/ N! g# \9 }( T

& J7 c6 z; {2 A. K1 hLow Pin Count Host Interface (LPC)
" w4 m# D2 R  C6 ^2 g# X) F5 B  SIRQ supporting IRQ1, IRQ12, SCI
' X# ~8 ]5 N; N: d" }( Q  I/O Address Decoding:, S2 C$ T% W) A
  KBC IO Port 60h/64h
: V/ o7 K4 {4 h0 x9 {  Programmable EC IO Port 62h/66h and 68h/6Ch6 P! U$ Q3 Z! t0 e# r0 T* X* c
  Programmable 4-byte Index I/O ports to access internal registers
2 f$ V6 e: @, z4 P  One Programmable I/O write byte-address decoding( m; D! v( z6 d# h

8 J1 a& l& b) d( c5 x# pX-Bus Interface (XBI)
- Z/ M4 n+ a! o  v  SPI Flash support, the operation frequency runs at least 50MHz.7 i" C! K$ G0 j3 O, c- o+ C
  Addressable Memory range up to 24MB.: ]) j2 a' J, {; }! q9 s8 z* T0 |
  8051 64KB code memory can be mapped into 4 independent 16KB pages.
/ I- x9 t* t+ r& c4 }8 a+ a! e# y- }  o1 K* X2 X$ ?: M% G7 U
8051 Microprocessor' w, `) L! {$ \. C
  Industry 8051 Instruction set complaint with 3~5 cycles per instruction.; S- W7 p% n9 Z
  Programmable 8/16/32 MHz clock& k; V5 S: s; S5 z- T
  Fast instruction fetching from XBI Interface
. n6 E) c9 [, Y$ X  128 bytes and 2KB tightly-coupled SRAM2 ^: Q1 x6 h# g' J  W- _  s- s
  24 extended interrupt sources.5 D/ Y& S" |) A' c+ x6 k5 X
  Two 16-bit tightly-coupled timer* ]" o  K7 ]' l6 Z0 U) G# b
7 O3 O! X" B( U- x! c( V
8042 Keyboard Controller
0 e9 X+ t7 k4 g$ s  8 Standard keyboard commands processed by hardware1 @% K7 L5 Q; K8 D7 J- O
  Each hardware command can be optionally processed by firmware8 L( V, [" H) W- N7 a, T
: k7 F4 Z# {" i/ I
Embedded Controller (EC)( w# x: N; W; E, J: }$ |" g* i
  Five EC Standard Commands can be processed by hardware
! L! c" J6 h& a! x1 T/ k  ACPI Specification 2.0 compliant
2 k0 k$ T% {2 L  Support customer command by firmware. A7 V# K( ]% U( M, U! \
  Programmable EC I/O port addressing (default 62h/66h)
& f, G" l2 }( Y/ R7 O3 O2 [$ O) M# ]/ F* y% |$ ]8 M7 ]5 S& I0 m
Analog To Digital Converter (ADC)
# z7 ^6 M9 w6 X3 m: c$ I7 P. ?- a  6 built-in ADCs with 8-bit resolution.9 j' q2 z; r4 E* @2 ^* k
  The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
7 H* g5 K" Q, K7 [
2 q5 Y, x9 T- `: d0 YPulse Width Modulator (PWM)5 g; ]( u! j5 t" C+ }! w1 T9 Z
  5 built-in PWMs3 k5 j) ^( X1 D/ A" W( r
  Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
. W3 z  O, p9 O% f) i- e  Configurable cycle time (up to 1 sec) and duty cycle.
! f% r2 g( Q) I( }" S  f
' e1 ~2 p' b( D5 }Watchdog Timer (WDT)0 D2 K! @2 s( w9 J1 R; g- H
  32.768KHz input clock with 20-bit time scale.# B1 F) M9 l$ ?! _
  8-bit watchdog timer interrupt and reset setting
% {. l' ~6 _8 B% h
! g  ^1 Z' R0 H5 f7 |General Purpose Timer (GPT)
& W- p6 d2 M- |% J0 i: f  Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
  \) D* |- j! H( T( K4 `: `. t/ T3 L3 I, _6 G, x& m8 V
General Purpose Wake-Up (GPWU)
9 n- {, ^( }) m# h- s  All General Purpose Input pins can be configured to generate interrupts or wake-up event.& |# e, X* c$ Y0 r. W  }

) x1 K8 ]. ^$ Q/ G" E# NGeneral Purpose Input/Output (GPIO); N) }( M5 X4 ^- s4 l- Q
  All I/O pins are bi-direction and configurable
+ N0 Q2 p, Q5 \& b  All outputs can be optionally tri-stated" e$ o& ]" w9 O3 ~
  All inputs equipped with pull-up, high/low active, edge/level trigger selection
* D  M: O$ T4 |  All GPIO pins are bi-direction, input and output.+ w4 F3 `2 A- N* e
  Max. 43 GPIOs
8 S" C; }2 x# q& o4 _: N: f3 Y* i7 C# Z- W
Power Management
% V( [0 V, r! d: }5 m4 V# v5 ^  Sleep State: 8051 Program Counter (PC) stopped
) I) l3 y# A7 f$ F3 i- U  Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.' I/ D: C- N/ B, N# K) k: W, q

0 b, {" \. k) ]0 W8 [9 aTotal Pages: 40

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发表于 2008-12-4 12:05:57 | 显示全部楼层
many thanks! 有KB3310的DATASHEET吗?
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发表于 2008-12-4 16:10:26 | 显示全部楼层
Thanks a lot
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发表于 2009-4-9 15:27:40 | 显示全部楼层
这个SPEC还是太简单了,谁知道ENE在用SPI ROM时,prefetch的cache有多大?如果spi run over 50Mhz,我看到它的8051处理指令需要3~5个cycles,而且听说ENE用的免费的C code,那么你们在用的时候感觉perfermance怎么样?特别是处理PS2 device的时候。
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