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Feature Summary
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$ c( b: N9 O: x3 |' e3 }Low Pin Count Host Interface (LPC)/ f" i, h7 H) K( u$ C( P1 [
SIRQ supporting IRQ1, IRQ12, SCI' @0 m* V# p3 R+ b1 ^' W
I/O Address Decoding:$ h2 L. Q! ?3 i, e
KBC IO Port 60h/64h" ^' `/ N1 u( Y* {9 f* s" a: y
Programmable EC IO Port 62h/66h and 68h/6Ch1 S Y9 N1 Q1 h2 _' \& E
Programmable 4-byte Index I/O ports to access internal registers
9 w7 q5 P5 Q( f- J One Programmable I/O write byte-address decoding
# _- [8 Y- E# `1 U. N! [& y! K7 p+ i0 y% S
X-Bus Interface (XBI)/ u! m$ \2 _. G; l8 O2 X
SPI Flash support, the operation frequency runs at least 50MHz.
# |& V3 o5 W3 r& l: H* V8 p6 ~ Addressable Memory range up to 24MB.
5 g" w( y: Q9 l [. K 8051 64KB code memory can be mapped into 4 independent 16KB pages.! h( B3 A$ P( m) I% P+ T+ _5 k; U
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8051 Microprocessor
+ S! X8 u8 ~: e$ n5 Z( D Industry 8051 Instruction set complaint with 3~5 cycles per instruction.
4 ?5 A2 _$ l: I7 x" o Programmable 8/16/32 MHz clock
, X+ N5 Z$ W% K0 C3 V) D% X1 Z Fast instruction fetching from XBI Interface/ \: F, a# b+ U, f7 r
128 bytes and 2KB tightly-coupled SRAM1 K1 d! g `& x+ Z( K% ]+ V) Y; _
24 extended interrupt sources.
/ Q; `2 b; K# m Two 16-bit tightly-coupled timer6 C* W3 t, J( @; u
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8042 Keyboard Controller
# J+ O! Z1 @; m- m( [3 P; ] 8 Standard keyboard commands processed by hardware2 }( A: G, O7 R9 P, u* a
Each hardware command can be optionally processed by firmware
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Embedded Controller (EC)1 k: ]9 {, _5 l$ l; B& ~' A
Five EC Standard Commands can be processed by hardware
, @1 D. t# |4 Q0 Z, M+ x, a ACPI Specification 2.0 compliant- W! P9 i. Q' Y' P/ a8 R
Support customer command by firmware( I; [- @, l% X/ T) r# ~
Programmable EC I/O port addressing (default 62h/66h); \! G9 `0 }0 H
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Analog To Digital Converter (ADC)
" z$ @" N5 _9 e V' M2 K1 g 6 built-in ADCs with 8-bit resolution.+ R# L2 i1 L. s7 j
The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
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Pulse Width Modulator (PWM)
# ~; ^% @ j$ S* A% k 5 built-in PWMs
2 E' e7 Y# K, n0 w; f Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
2 R7 a5 `! f; z% `2 o Configurable cycle time (up to 1 sec) and duty cycle.
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Watchdog Timer (WDT) q: b! j% \7 e" t/ p. G
32.768KHz input clock with 20-bit time scale.0 W: k6 v) n; u- L
8-bit watchdog timer interrupt and reset setting4 t. \4 T+ H4 R
) O) ^; x1 x8 m- q; `6 f# Q+ \# wGeneral Purpose Timer (GPT)
6 P0 j$ t0 {. \0 o" w. H Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
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General Purpose Wake-Up (GPWU)
+ H# p1 x5 }2 [0 g9 g( r U All General Purpose Input pins can be configured to generate interrupts or wake-up event.
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! |+ C' C: F1 `9 VGeneral Purpose Input/Output (GPIO)
; u/ f* S. i6 Z' r R2 L All I/O pins are bi-direction and configurable
0 W" s! R1 o, P- P( t! U, `; a4 | All outputs can be optionally tri-stated3 l# T$ G9 P/ g2 Q/ B& U% _5 E. y
All inputs equipped with pull-up, high/low active, edge/level trigger selection
% O% e$ ^' M% p0 P) W3 { All GPIO pins are bi-direction, input and output.3 p4 {1 O! w4 U- e7 G6 ]6 q' G
Max. 43 GPIOs
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# p6 j. {$ J& x, {Power Management6 x7 D2 [; W. I' r/ @* u% X
Sleep State: 8051 Program Counter (PC) stopped/ n' \' f2 _* M
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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0 s1 t: ?9 l1 B/ _: h ~! aTotal Pages: 40 |
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