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Programming Interface for Bus Master IDE Controller Revision 1.0
5 Y8 U. {8 C6 h0 L# a1994/05/166 D1 v9 s/ R! z: Y, u5 }$ i
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
0 Q% t2 o' N) t" ~7 I) icontroller that directly moves data between IDE devices and main memory. By performing the IDE data
+ K) ^0 R0 ^( W5 l, G' V) ] jtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
8 H4 y+ f+ W/ |, l$ Kand improves system performance in multitasking environments.: x& |7 d' R% n$ s( z
2 C/ u) ?6 I5 MUntil this specification is ratified, it is solely3 z9 V# c& e/ g; _- E
owned and maintained by:
1 W: m* w% f: u" R$ [! WBrad Hosler, Intel Corporation8 J0 n4 M% @: x1 j! z2 F. w4 q
bwh@salem.intel.com (please comment using email)/ k8 F9 V; c1 T$ r- W" V3 q
503-696-8431 |
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发表于 2010-7-14 14:53:56
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