|
Programming Interface for Bus Master IDE Controller Revision 1.0; ^2 a$ i) Q0 q& R$ g$ L% b; q
1994/05/16. W( K( d8 V; j& n. D
- b& |1 H% p/ P, w* t+ \$ ~
This document defines a register level programming interface for a bus master ATA compatible (IDE) disk+ w& E2 K* X7 v) r0 N$ L. g
controller that directly moves data between IDE devices and main memory. By performing the IDE data! q4 [" L4 d+ s& K1 {* ?2 ?: _
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
3 |* {! o( c; Tand improves system performance in multitasking environments.
5 ]) U( n; n! ]9 e Q& C
9 R" v$ o% b! V/ |6 xUntil this specification is ratified, it is solely& R& A" t: R/ n
owned and maintained by:
! |" v/ e e) j- CBrad Hosler, Intel Corporation
6 f4 p. Y3 {8 K2 p5 Xbwh@salem.intel.com (please comment using email)6 {$ s$ U T6 V+ A4 z
503-696-8431 |
|