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Programming Interface for Bus Master IDE Controller Revision 1.0, C/ x" |8 m5 B; A
1994/05/16: F- s% f& D. x& E6 j3 t0 z
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
7 L2 n% h. ?! lcontroller that directly moves data between IDE devices and main memory. By performing the IDE data
. H4 J- z: X4 E9 }, ]transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)3 w3 m7 t% X4 j$ W+ Q
and improves system performance in multitasking environments.4 M) Q8 {1 I6 h+ z1 c
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Until this specification is ratified, it is solely- k! H8 Y ]* O! Z0 E, e+ u/ b
owned and maintained by:
' J# @& p6 |8 B: u9 [- zBrad Hosler, Intel Corporation- d4 K) \/ x6 M; T7 U0 ^( [
bwh@salem.intel.com (please comment using email)8 D7 P' ] X1 g- g' I
503-696-8431 |
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