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Programming Interface for Bus Master IDE Controller Revision 1.0! [' J: ^3 }: s+ V( d
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
5 y0 t ~; e: X0 T6 R( g+ L8 _controller that directly moves data between IDE devices and main memory. By performing the IDE data
" u& k7 o5 s$ Itransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)* y/ H! O2 o* u; j s
and improves system performance in multitasking environments.
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: x! {5 U3 s+ l/ y M, OUntil this specification is ratified, it is solely1 i; W( P5 K9 C( _
owned and maintained by:
" ], q$ W: Q1 |7 F5 OBrad Hosler, Intel Corporation& G6 M* J) d% [2 g! ~6 q
bwh@salem.intel.com (please comment using email)
% o6 Q3 p& z7 M" s503-696-8431 |
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