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Programming Interface for Bus Master IDE Controller Revision 1.0
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk1 f$ r& `! Z/ D! r, z* G
controller that directly moves data between IDE devices and main memory. By performing the IDE data
& J. n1 o! l: K5 Ztransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)7 Q: B. l! Y- E" L" S) }7 M" B
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely6 C P& I( D: x2 \1 Z) s0 r
owned and maintained by:
1 n% \/ x% X6 k3 s; `Brad Hosler, Intel Corporation+ ]& h. \ I) E! E a' N
bwh@salem.intel.com (please comment using email)2 z8 W/ w( I) [. d
503-696-8431 |
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发表于 2010-7-14 14:53:56
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