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Programming Interface for Bus Master IDE Controller Revision 1.0, D; S+ T3 ~1 a
1994/05/163 @" q7 g$ W2 e# Z
' H+ T- b+ Z; C$ P/ cThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk6 [. I! T3 M/ y2 A) Q
controller that directly moves data between IDE devices and main memory. By performing the IDE data
, @, z7 t! Z* \; Jtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
, F# D" j" V0 I* g# iand improves system performance in multitasking environments.- E6 `% ^8 H4 `; W1 M% t8 X8 t
1 m' n v% [0 ]2 k4 h4 `( j7 ^/ C8 k
Until this specification is ratified, it is solely: ^" S/ y8 P% [
owned and maintained by:# V! `: ~$ n3 D6 [/ X, \+ g
Brad Hosler, Intel Corporation2 J8 D; a. Q1 ]& ?, ^
bwh@salem.intel.com (please comment using email)
! e# [- ~; w$ g8 d+ g) K503-696-8431 |
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