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Programming Interface for Bus Master IDE Controller Revision 1.06 Z6 a$ D" T0 r& V& k2 w
1994/05/16
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1 z9 N; D$ x0 l/ {This document defines a register level programming interface for a bus master ATA compatible (IDE) disk: l* s" i" m! U3 h, t8 F0 l
controller that directly moves data between IDE devices and main memory. By performing the IDE data
3 m) T. p' }- wtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)# o/ f9 B. w3 [5 {0 Z
and improves system performance in multitasking environments.0 }# K, x J+ Q* @) p: c) e5 f) T* O
. Q' P0 r/ t) F7 ~, w2 cUntil this specification is ratified, it is solely
; y+ b$ `" F5 W4 H- U/ Yowned and maintained by:1 b' B- m8 V2 G3 H/ k6 `7 b) ?
Brad Hosler, Intel Corporation3 y" `$ r# e6 d+ ~. C' ]
bwh@salem.intel.com (please comment using email)
& k( e# {; o$ m# h" v3 m503-696-8431 |
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发表于 2010-7-14 14:53:56
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