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Programming Interface for Bus Master IDE Controller Revision 1.0
" G- W; ~' ~2 ]1994/05/16; o- x' ]' v1 i' P9 f
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
' T2 h! }" W$ d7 s4 i* ncontroller that directly moves data between IDE devices and main memory. By performing the IDE data4 R1 u1 R1 {7 R8 m w. M) X. J
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)/ e4 n& m; y# o% v# [( T
and improves system performance in multitasking environments.7 q$ |, {. S% e# d, ^
1 {9 I% C1 ~+ M( C* `. _8 o9 l: B& fUntil this specification is ratified, it is solely# g; e3 p4 h. ]9 M* b! w* j; ^
owned and maintained by:1 k4 a( t$ c0 X4 _: j
Brad Hosler, Intel Corporation$ U; e* {2 v6 Q" C
bwh@salem.intel.com (please comment using email)
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发表于 2010-7-14 14:53:56
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