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Programming Interface for Bus Master IDE Controller Revision 1.0! X# Q% p# ^. X5 c
1994/05/16/ f/ Y" Z8 {6 R9 l" N4 M' S# H
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk4 w" d d- K/ x0 j
controller that directly moves data between IDE devices and main memory. By performing the IDE data
2 \+ t: g2 y$ Y1 {' S. P( B6 atransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer); K5 S* l2 }0 h3 s3 e$ {
and improves system performance in multitasking environments.0 W9 h) `' I0 ^) m ]5 k {) z
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Until this specification is ratified, it is solely+ g2 w$ P. g& c: J
owned and maintained by:8 Z* p2 T% v0 j% F* x) y
Brad Hosler, Intel Corporation/ n* N8 J: M) h% c" ]9 V
bwh@salem.intel.com (please comment using email)/ T8 Y- H O4 W; f" X E# C
503-696-8431 |
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发表于 2010-7-14 14:53:56
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