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Programming Interface for Bus Master IDE Controller Revision 1.03 o6 {" Q8 h$ e+ h3 k
1994/05/166 z {2 a# A0 o6 S+ R
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk* {+ [7 P9 F4 |4 ?5 S2 N
controller that directly moves data between IDE devices and main memory. By performing the IDE data
( T* n+ Z' s4 T( u( htransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)2 ^) L1 n9 a! v* u. r) W
and improves system performance in multitasking environments.
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) |# H: t1 v J: _( CUntil this specification is ratified, it is solely/ z( z) J U+ [+ D
owned and maintained by:' h, F0 I S4 a6 Q C
Brad Hosler, Intel Corporation
a- C. W$ j1 ubwh@salem.intel.com (please comment using email)' h, Q' Z8 z/ {: \8 e1 |# l: u* y
503-696-8431 |
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