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Programming Interface for Bus Master IDE Controller Revision 1.0
: E: m3 g( W& j, D1 H. N1994/05/16
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9 R/ _9 r. q" t2 c1 GThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk* m7 z8 `* c% I, {
controller that directly moves data between IDE devices and main memory. By performing the IDE data
1 E2 O, w: i# I& Z; ftransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)' D ?. C+ w6 y1 ~0 K! Q
and improves system performance in multitasking environments.3 Z$ ^7 i- L8 O4 D9 t
5 z1 ?6 A- S* fUntil this specification is ratified, it is solely
( y" l: @/ {6 s( f8 Y5 W Towned and maintained by:% U- d1 M/ w9 S7 ]3 Q$ Y# W
Brad Hosler, Intel Corporation; O; \9 O7 O3 h3 g) P9 G
bwh@salem.intel.com (please comment using email) `9 V: S- r' `3 k
503-696-8431 |
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