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Programming Interface for Bus Master IDE Controller Revision 1.0
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk& V' N- O! \$ }: n5 V4 N3 q( ^6 f
controller that directly moves data between IDE devices and main memory. By performing the IDE data
4 r- c8 E2 r6 d, v( n6 ~+ o' g2 Ttransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer) }; u! Y m1 y1 u5 [) h$ ?$ g
and improves system performance in multitasking environments.7 Q3 o# y( @$ J1 K6 M* G' V0 O
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Until this specification is ratified, it is solely
+ g& X& ]8 m1 xowned and maintained by:7 _4 M9 X% w- H1 B
Brad Hosler, Intel Corporation
l' _0 Q+ F! h/ B5 b- ~0 Z1 o" Gbwh@salem.intel.com (please comment using email)5 v8 v7 ]1 o8 |; v" g- q
503-696-8431 |
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