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Programming Interface for Bus Master IDE Controller Revision 1.0
; L5 f' {; X( h- `1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
d( C$ X0 c% U# W3 P/ e! qcontroller that directly moves data between IDE devices and main memory. By performing the IDE data; w" I* }: h V+ [
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
) s* L9 H( b Oand improves system performance in multitasking environments.
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Until this specification is ratified, it is solely
1 P8 G E4 C2 Z, Yowned and maintained by:: |% C, |; U1 L9 H/ b A
Brad Hosler, Intel Corporation( w5 \# N$ [( u$ d6 ]# f; ?
bwh@salem.intel.com (please comment using email)
+ v6 V, f) @8 j0 i/ H2 a2 u* b# ?503-696-8431 |
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