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Programming Interface for Bus Master IDE Controller Revision 1.00 _0 I( _) H! y. {
1994/05/16
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; {0 K% {( m. U# K$ GThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk) a. S5 K# F' I5 W: f; J
controller that directly moves data between IDE devices and main memory. By performing the IDE data/ ]( p( L7 x' E( n2 A; g0 `8 O7 i
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)" u( Q( X" r7 A# U) c+ w' m& e
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely
# n" l! Q5 x2 c+ jowned and maintained by:
3 h5 J: p `6 D' J! q2 d7 JBrad Hosler, Intel Corporation+ J! A) _5 X2 n% w
bwh@salem.intel.com (please comment using email). T# O+ X f+ I, }
503-696-8431 |
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