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Programming Interface for Bus Master IDE Controller Revision 1.0
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk( G1 M9 s! r7 y/ [) t4 z
controller that directly moves data between IDE devices and main memory. By performing the IDE data
. x( d2 U( q3 o$ L. b# k& vtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
4 l: U- ^+ F/ Y' {! ?0 l0 mand improves system performance in multitasking environments.
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8 o1 q. i! @& Y) ^0 fUntil this specification is ratified, it is solely+ [7 R- ~/ @$ ~2 [
owned and maintained by:
/ Z( Y( n9 X+ G/ Z9 aBrad Hosler, Intel Corporation# a! L3 }: ^0 F6 h
bwh@salem.intel.com (please comment using email)9 j, _% B3 r# M5 J( n
503-696-8431 |
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发表于 2010-7-14 14:53:56
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