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Programming Interface for Bus Master IDE Controller Revision 1.0& R) j x% O# g
1994/05/16) r( Q/ z/ D2 r- T4 O; [# w- b
2 }; \9 r$ W9 d; X/ QThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk( u6 ], Y7 D) F
controller that directly moves data between IDE devices and main memory. By performing the IDE data3 H7 k' A- W- F' a
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
0 c- g: i/ }$ r: Pand improves system performance in multitasking environments.. X j) C/ ?! L" |# Y" @, p
) m% ~! W4 B' ~2 VUntil this specification is ratified, it is solely
7 ]+ F! F( H$ ]) r8 v% j+ A' h9 E- towned and maintained by:, Z [2 C& Y" ^ {7 O0 S& W# [
Brad Hosler, Intel Corporation
- j7 i a4 X, dbwh@salem.intel.com (please comment using email)
`1 p. j$ ~! _, b9 ^6 Q503-696-8431 |
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发表于 2010-7-14 14:53:56
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