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Programming Interface for Bus Master IDE Controller Revision 1.0! @* n. v$ y+ |+ K2 c
1994/05/16
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9 g' K5 C; c' i+ ?This document defines a register level programming interface for a bus master ATA compatible (IDE) disk# t/ O9 K& V# j: k" _' y" {
controller that directly moves data between IDE devices and main memory. By performing the IDE data
' T* x: u6 p6 N7 u( I1 itransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)! }# D/ }% g4 M: K2 Z+ y/ _
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely
3 w ~7 w3 M7 {' J8 n/ a: S! Aowned and maintained by:
9 ^* ~ _' h* h- s) MBrad Hosler, Intel Corporation( C& w ^- u' W2 Z% _- r V
bwh@salem.intel.com (please comment using email)
2 ^. d @; t3 t: W/ y" k: G503-696-8431 |
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