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Programming Interface for Bus Master IDE Controller Revision 1.0# ]% O- T$ T9 N) u( g
1994/05/16
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8 U) ]" ` q4 q+ K0 M- IThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk7 \" T3 \6 W! i) k
controller that directly moves data between IDE devices and main memory. By performing the IDE data
: q) J3 N0 Z& Z& Jtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
) |0 P/ V6 `( [8 N3 u( J0 gand improves system performance in multitasking environments.3 c1 V8 ~, A- ?. g6 S; o7 C7 e
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Until this specification is ratified, it is solely: _9 y* O6 A& Z9 C2 g. |% P# R u
owned and maintained by:
$ s- ]* x. \1 kBrad Hosler, Intel Corporation, k/ w9 c/ j" ~" |
bwh@salem.intel.com (please comment using email)
* Y; j+ t* C' }1 Z7 d: L) A503-696-8431 |
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