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Programming Interface for Bus Master IDE Controller Revision 1.0 l8 ^ e x; n" n
1994/05/16
* X) _# G- p$ a }& j$ ^, e
, N" q- L- I) Z2 o* U# GThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk
/ Q, X) Z$ k: _" `controller that directly moves data between IDE devices and main memory. By performing the IDE data
) O0 Y* m1 w$ Ztransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)9 c# q& C9 M! L2 C( H
and improves system performance in multitasking environments.% P1 C2 g/ R" \5 B7 o& N
3 @! T% w! R$ f' W+ F
Until this specification is ratified, it is solely$ |, l0 Q6 d$ _# N$ S! R
owned and maintained by:
* M3 q: f8 [5 z; KBrad Hosler, Intel Corporation" `7 K3 ?+ n* f4 g V& {: t2 O" d% s
bwh@salem.intel.com (please comment using email)1 U% ~% c# M7 J3 l0 p) n$ R. V
503-696-8431 |
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