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Programming Interface for Bus Master IDE Controller Revision 1.01 I5 p0 f6 K" V1 j
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk. |2 ]5 o# G7 O2 V
controller that directly moves data between IDE devices and main memory. By performing the IDE data
& _' H4 J# C3 c2 B2 G5 T% }transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
& B* ~4 k& ^6 \1 {/ fand improves system performance in multitasking environments.
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; d/ j+ d, [( r: C( [% SUntil this specification is ratified, it is solely$ V0 Z' a5 z$ T2 i# I( p
owned and maintained by:( E8 M/ r. v! h' t* B) u$ [0 v& j- a
Brad Hosler, Intel Corporation# n( C. ~5 |3 t8 J% A( [) O7 {4 D, @
bwh@salem.intel.com (please comment using email); ` C$ E1 N# r8 E8 u" I& b8 S
503-696-8431 |
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