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Programming Interface for Bus Master IDE Controller Revision 1.07 b! m" O: C b
1994/05/16
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/ {* N) h0 X# M4 D2 Y# x3 yThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk
5 G8 r& M1 M i7 `) ~; r4 W0 ycontroller that directly moves data between IDE devices and main memory. By performing the IDE data
4 a' G e! T5 m! j. C* i) \3 Ktransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)% d1 u" x9 \3 ]4 ^# }8 M/ T
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely4 i; X0 U! _, f9 M- j
owned and maintained by:) [$ \+ z6 m% }& J
Brad Hosler, Intel Corporation
8 H/ C+ e, n! y8 k" Ybwh@salem.intel.com (please comment using email)
4 n8 g9 l& O4 q503-696-8431 |
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