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Programming Interface for Bus Master IDE Controller Revision 1.0. N, \" c E( [) Z1 `
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk' O" r- L1 ], U9 f
controller that directly moves data between IDE devices and main memory. By performing the IDE data
) B) s' y6 z# N1 ^1 G# \1 D4 rtransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
$ b8 z1 R% w5 i2 ^and improves system performance in multitasking environments.
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' B- f. c j: MUntil this specification is ratified, it is solely# @( p5 ]5 j" A- @
owned and maintained by:( @) A/ X+ U) D- p! @
Brad Hosler, Intel Corporation
! l) I( C/ Z" Q; bbwh@salem.intel.com (please comment using email)
7 C3 H2 O5 q- h( ]0 W7 j503-696-8431 |
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