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Programming Interface for Bus Master IDE Controller Revision 1.02 F! K! ?* R3 K" \
1994/05/16
5 F! E, x. m6 u
. {, s# k# n! @0 wThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk
* n0 j: ?+ F3 Rcontroller that directly moves data between IDE devices and main memory. By performing the IDE data$ R- \; l* Z- |; e
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)5 x6 @4 g! U2 f
and improves system performance in multitasking environments.6 l% F7 x7 y5 c; }
+ H5 U7 b* e9 P' \9 \
Until this specification is ratified, it is solely
2 q+ [, J) T5 ~* F3 e% Qowned and maintained by:
* i: q# B- W+ ~Brad Hosler, Intel Corporation
. e" w" R- s4 L1 V" b' j4 q- Zbwh@salem.intel.com (please comment using email)7 V" m8 x4 l7 o
503-696-8431 |
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