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Programming Interface for Bus Master IDE Controller Revision 1.0
% z& P. a4 J9 } M* \6 [1994/05/165 Y- ?% G) `# y
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk) N1 R, }' ]; L( E3 A# v# A u
controller that directly moves data between IDE devices and main memory. By performing the IDE data* O6 `: H$ H; f7 p7 L% P
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
6 X/ s, h. A* S% o6 a' s6 Sand improves system performance in multitasking environments.& d$ ?2 K3 q) I! U- a! X) w
! j6 v' z. p% n2 eUntil this specification is ratified, it is solely
: l I* l9 D3 F4 ~: p- L6 mowned and maintained by:( I# F9 l. l9 j! m( d# p! h
Brad Hosler, Intel Corporation
; Y9 ~3 p0 @/ m0 c; m3 ebwh@salem.intel.com (please comment using email)5 Q! B q3 |2 G% T$ o; C; c
503-696-8431 |
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