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Programming Interface for Bus Master IDE Controller Revision 1.0
1 P. j( ]$ o! t% c9 Z9 r% k/ Q1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
& M0 p% O" w6 econtroller that directly moves data between IDE devices and main memory. By performing the IDE data& b) |% n S4 p C+ O3 B2 m
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer). l2 H+ P/ d" {7 q. \4 b' I; G
and improves system performance in multitasking environments.
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4 `: W: w( m" p$ rUntil this specification is ratified, it is solely
6 j! f- K; S% x% D. Fowned and maintained by:
9 d2 |& `! R) S$ O3 z) jBrad Hosler, Intel Corporation
) C) `* j- Q6 B/ F/ q: E' _bwh@salem.intel.com (please comment using email)
' H/ r: O4 ?0 a5 a503-696-8431 |
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