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Programming Interface for Bus Master IDE Controller Revision 1.0
+ k( J |4 u: k2 r1994/05/16
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) Q! O( _ N( ?& c$ \+ xThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk7 Z- Y8 u# X' f8 w
controller that directly moves data between IDE devices and main memory. By performing the IDE data
% y- |. r ?1 X, R4 M) M+ K2 etransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
- P! x0 \# a wand improves system performance in multitasking environments.! ^; k" d% e" {
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Until this specification is ratified, it is solely
. I- i. h) d- m" M- {/ Q1 O1 |owned and maintained by:1 e7 g2 Y; x6 p9 E- v' k
Brad Hosler, Intel Corporation$ k/ v6 x$ l$ |, W4 k) v0 q$ ?1 Z
bwh@salem.intel.com (please comment using email)
, \: A3 J5 e$ A7 h/ r503-696-8431 |
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