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Programming Interface for Bus Master IDE Controller Revision 1.0! f$ n, T. W. }" H C
1994/05/16
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: e+ W' r! G& n% _: _7 I8 {+ \This document defines a register level programming interface for a bus master ATA compatible (IDE) disk% C5 F: h& W* k8 ]4 S1 M
controller that directly moves data between IDE devices and main memory. By performing the IDE data9 o* p" ~! O' y% _4 S0 A
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)- x# h! P% [1 [0 [4 s
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely
; z u; @* d: [& } f9 B6 towned and maintained by:" ^ W+ N5 e* q3 N( V A
Brad Hosler, Intel Corporation- [: o$ F: U. b4 [# X0 w3 f+ M
bwh@salem.intel.com (please comment using email)5 O4 S8 z# d G2 X6 Y( }" I* w
503-696-8431 |
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