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Programming Interface for Bus Master IDE Controller Revision 1.0/ _3 {% j* T6 O9 \- G
1994/05/166 l1 v2 r( L* o4 g2 S
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk2 Y9 W! ]" R, ~$ A" H* o2 k! h
controller that directly moves data between IDE devices and main memory. By performing the IDE data
8 G& w" r' ?0 n; p1 M& j# E5 Ttransfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)' f* H, `! `8 @/ ^
and improves system performance in multitasking environments.
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Until this specification is ratified, it is solely5 p0 P$ N9 ?2 G* b. G
owned and maintained by:" o3 Q- z/ M7 Y) x" d
Brad Hosler, Intel Corporation. n9 u* n+ F! l3 |" o3 T5 v
bwh@salem.intel.com (please comment using email)
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