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Programming Interface for Bus Master IDE Controller Revision 1.0% ?2 y2 f9 O9 g( i9 u: t8 {8 k
1994/05/16
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This document defines a register level programming interface for a bus master ATA compatible (IDE) disk
* ?# `+ I+ [8 M, h, d- Ocontroller that directly moves data between IDE devices and main memory. By performing the IDE data/ X3 q1 I6 a' D- _- `+ a+ W4 u2 } D
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
8 g- J4 R. x' F3 f: d# fand improves system performance in multitasking environments. L/ z/ F8 f" Q: n$ r4 }1 l( n
% ~) `: \2 y, c0 ^* U5 mUntil this specification is ratified, it is solely
1 f* z) M% b! ~1 B! J$ Q- e1 v5 Mowned and maintained by:
- x9 V% b' u2 L2 O* L3 H" XBrad Hosler, Intel Corporation
# d% d& g' X0 x x W4 Pbwh@salem.intel.com (please comment using email)( r0 ?0 A7 o% i% O G8 ^! V
503-696-8431 |
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发表于 2010-7-14 14:53:56
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