Programming Interface for Bus Master IDE Controller Revision 1.0

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Programming Interface for Bus Master IDE Controller Revision 1.0
. H. o# W- P4 ~' l: c2 i1994/05/16

/ X* C4 l5 G' P! q5 M* N1 KThis document defines a register level programming interface for a bus master ATA compatible (IDE) disk
# `" a/ u3 b) N2 q) Y, |controller that directly moves data between IDE devices and main memory. By performing the IDE data
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
and improves system performance in multitasking environments.
2 [9 ~2 _8 ?* w, d
Until this specification is ratified, it is solely
6 ^& }* L  w/ Z: J" v6 b9 r/ l, xowned and maintained by:
2 y2 O7 `* W6 P# U  CBrad Hosler, Intel Corporation
bwh@salem.intel.com (please comment using email)
) ?  _3 F7 z) K, h( b4 j8 R503-696-8431