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Programming Interface for Bus Master IDE Controller Revision 1.05 E* m4 d" j% b& q. P- K. a) q- G" W
1994/05/16" Q2 L X0 U; I. Z; c& _. T
4 Z1 c. W! M7 _ Y5 c% v
This document defines a register level programming interface for a bus master ATA compatible (IDE) disk8 c3 L; G, o+ o% ~1 j# b
controller that directly moves data between IDE devices and main memory. By performing the IDE data- b+ E: f# J" h7 F
transfer as a bus master, the Bus Master Device offloads the CPU (no programmed IO for data transfer)
: T2 v& D6 s: w' v$ T. G$ U, Aand improves system performance in multitasking environments., X! v' u5 j/ x% i
3 D" V2 s3 {3 G& ` qUntil this specification is ratified, it is solely
$ ^! ?; t) J/ U# R l1 kowned and maintained by:4 V$ x/ Y% J* {( E+ V7 E
Brad Hosler, Intel Corporation/ v; n( e5 Q& }1 ~$ V4 b
bwh@salem.intel.com (please comment using email)( w! V4 R- m* o
503-696-8431 |
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发表于 2010-7-14 14:53:56
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