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CPU Reset 后的前100多条指令
, ~4 f6 w0 m4 `, F5 ?6 [测试平台: Intel Menlow Crown Bench CRB
+ S2 }& \) I' |& RBIOS: 自带的 AMI BIOS
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Below is the instruction and registers when CPU reset
8 q! L- O# t/ F1 \6 X2 f0 X. rF000:0000FFF0 EAAAFF00F0 JMP far16 ptr f000:0000ffaa4 O( K. W/ b0 ~% G4 H: Y" _
EAX = 00000000: AX=0000 AH=00 AL=00
& a. \2 O0 i' d- l9 e$ w) p" _EBX = 00000000: BX=0000 BH=00 BL=00
' h0 A$ m" }' X% FECX = 00000000: CX=0000 CH=00 CL=00
# b6 V3 T( K4 V. u: L- hEDX = 000106C0: DX=06C0 DH=06 DL=C0
( P# `2 m) Y. S: ~9 C9 cEBP = 00000000: BP=0000 , b- `- i& }# m6 q
ESI = 00000000: SI=0000
: o2 q! S1 j# c. s5 {& p1 gEDI = 00000000: DI=0000
- _$ K, u$ o9 R1 B+ o( BESP = 00000000: SP=0000 " f) L- c8 b4 D% L; k- @( o
CS = F000
9 a% m: {4 J5 eDS = 0000# G/ R1 o. x3 h/ \. K" h
SS = 0000
& J7 b# _$ ~# l K5 ?( GES = 0000
5 C/ ?' m& S3 _5 f* M! pFS = 00004 F- i& O7 r u9 M
GS = 0000
" i3 H; G. U6 I# |EIP = 0000FFF0: IP=FFF0 : ?3 p) u% w0 P! i% [; E0 @, r
EFLAGS = 00000002: FLAGS=0002 ID=0 VIP=0 VIF=0 AC=0 VM=0 RF=0 NT=0 IOPL=0 OF=0 DF=0 INF=0 TF=0 SF=0 ZF=0 AF=0 PF=0 CF=0 * S+ G% A; m$ d& v3 Q
CR0 = 60000010: PG=0 CD=1 NW=1 AM=0 WP=0 NE=0 ET=1 TS=0 EM=0 MP=0 PE=0 - `' U; P. r; F. A' I& C, h
CR2 = 000000007 J p" `/ E$ z3 p
CR3 = 00000000: PCD=0 PWT=0 ) a1 [/ m. Z7 [. R
CR4 = 00000000: VMXE=0 OSXMMEXCPT=0 OSFXSR=0 PCE=0 PGE=0 MCE=0 PSE=0 PAE=0 DE=0 TSD=0 PVI=0 VME=0 + P, `& [& l9 a! n2 A
# P$ t3 [$ R3 B0 n8 m' S8 WInstruction for CPU step 00
3 K8 B" A- S* }" m# iF000:FFAA E9C300 JMP near16 ptr 0070; N8 x' p$ x2 @* v
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Instruction for CPU step 01
2 C, t( _( ]$ Y; G+ O z0 Z" KF000:0070 E9FD01 JMP near16 ptr 0270
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+ g" s0 g$ C3 X+ p* M8 W. g, jInstruction for CPU step 02( u' n4 \: n* M0 ~. X; ]3 n
F000:0270 FA CLI
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Instruction for CPU step 03
Y; D0 K& R% nF000:0271 FC CLD 0 X+ E" O6 j5 H: I, A* B1 M
& |9 `6 L: W7 q' t, _Instruction for CPU step 04
. Y7 F, g! y5 v3 |4 ^) L" | YF000:0272 668BE0 MOV ESP,EAX
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Instruction for CPU step 05% B q1 I" b+ H% E/ I' C! a
F000:0275 8CC8 MOV AX,CS
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Instruction for CPU step 065 a2 {' o6 R7 c, g
F000:0277 8ED0 MOV SS,AX ' |; r+ T' _, N' ~% Z
& r; }, K) x4 X6 }Instruction for CPU step 07
; l4 O9 O ?' N5 l8 ]8 l9 bF000:027C E957FE JMP near16 ptr 00d6
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Instruction for CPU step 08/ @/ C R; b1 V% i
F000:00D6 E9A601 JMP near16 ptr 027f
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Instruction for CPU step 097 U! f g& E7 ~7 q9 p
F000:027F B0D0 MOV AL,d0
2 [2 [" n, ]6 O5 x * |% F+ C' \- [
Instruction for CPU step 10
% z" Z/ b5 E* b2 T, L1 NF000:0281 E680 OUT 80,AL 4 U g2 @9 a5 M8 K) \+ J+ N0 v
- M- Z7 j( A7 I" I+ lInstruction for CPU step 117 C, Z9 Y4 E9 Y; D5 `1 H+ Z: R) S' Y
F000:0283 BF8902 MOV DI,0289
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. [, a& K: z3 Q; MInstruction for CPU step 12$ A9 Z5 d7 G( U. H
F000:0286 E9AE06 JMP near16 ptr 0937
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9 ] G+ }4 J9 qInstruction for CPU step 13
0 t3 w* T3 e+ W' M7 L2 ~F000:0937 0F08 INVD
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5 @' B4 B" m8 k1 I& ~Instruction for CPU step 14
% L9 i G! P- Z% r# j# JF000:0939 0F6EFF MOVD MM7,EDI 2 C Z/ d4 o; C; s% r" [
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Instruction for CPU step 15
4 t: i7 N! b4 t6 I( T) L, oF000:093C 668BC4 MOV EAX,ESP
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* y6 P: K# {5 r$ ^; C' iInstruction for CPU step 16- W( L: n2 o( j8 S/ K
F000:093F E97C08 JMP near16 ptr 11be
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Instruction for CPU step 17. [+ D$ N0 t' T0 X1 m
F000:11BE E981F7 JMP near16 ptr 0942* |# R7 b, Y# }" R+ Q; B
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Instruction for CPU step 18
% w+ d0 }$ z$ m) b( gF000:0942 BF4809 MOV DI,0948
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0 D6 v O, d' q7 n/ h/ r* wInstruction for CPU step 19" K* V9 s; h- I" S! c0 K
F000:0945 E9C004 JMP near16 ptr 0e08) ^. ^* }; s/ ?& Y4 l& w
6 i+ L' i/ F3 j XInstruction for CPU step 20/ T8 e5 N" t$ ~6 K! M0 N
F000:0E08 0F20C0 MOV EAX,CR0 0 p6 B6 @. P3 \5 L. @$ d4 ^) l
' X) V U, ], wInstruction for CPU step 219 T( P0 M X4 n. G; _
F000:0E0B 660D00000060 OR EAX,600000001 G S; w+ T# Y4 G ]1 W
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Instruction for CPU step 22
- s6 O q) N/ }1 M1 c+ ^' N5 o' T T3 jF000:0E11 0F22C0 MOV CR0,EAX + S6 j4 p* h# v f
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Instruction for CPU step 23
& Z1 m7 B( `: c$ K' F. i- g- AF000:0E14 0F09 WBINVD , M# t: ~! I. u& u7 r- t" {9 {
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Instruction for CPU step 24
1 [2 v! D! k" a. QF000:0E16 66B9FF020000 MOV ECX,000002ff4 {- |+ n+ ~* a
% T+ n5 o4 s% H7 Y0 l% jInstruction for CPU step 25 Y8 Y2 [' C$ g# A$ R ~
F000:0E1C 0F32 RDMSR
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0 e9 L L* Z% C# VInstruction for CPU step 26
6 q( h P; J* \( {F000:0E1E 25FFF3 AND AX,f3ff % p) O7 X3 S# c( o/ F* Q
: \! W8 E8 R' kInstruction for CPU step 27
: r( v+ h: i6 `F000:0E21 0F30 WRMSR
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Instruction for CPU step 28; y, ~! ?! \, d6 W# \8 h& }
F000:0E23 0F09 WBINVD
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Instruction for CPU step 29
9 G# Y% y8 e K5 I* x2 xF000:0E25 0F20E0 MOV EAX,CR4 6 E1 S2 |* R% T; y% B3 U
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Instruction for CPU step 30
* u% `) W" i* O. x x: H$ U( yF000:0E28 247F AND AL,7f 1 n; }# C, N9 I+ z3 g$ Z% e
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Instruction for CPU step 31
" A1 S4 d% u3 ^F000:0E2A 0F22E0 MOV CR4,EAX 9 y3 n4 _) E. w, C- i0 A
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Instruction for CPU step 32
# Y2 _3 b4 S, [0 y# _F000:0E2D 0F20D8 MOV EAX,CR3 0 @. ?% ~ ~" I' F
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Instruction for CPU step 33* L, C4 W. J) t& v$ C4 t7 ^
F000:0E30 0F22D8 MOV CR3,EAX $ z/ v6 N! P5 y+ w0 {3 U- _$ {
4 a# v& _' C% P+ C2 r JInstruction for CPU step 34' E5 D+ Y2 a, r: t) E% D
F000:0E33 FFE7 JMP DI 2 C4 v) E2 {' N! |
# U- }0 d, T& ~+ wInstruction for CPU step 35# X5 [' J: }3 D
F000:0948 66B9FE000000 MOV ECX,000000fe
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Instruction for CPU step 36
4 |3 d. s/ m! bF000:094E 0F32 RDMSR 8 D8 S! C9 E' |' k6 N/ R
7 f9 P& u- k0 tInstruction for CPU step 37
- j- x' ~% k7 `, V; B1 l2 l, f5 q) ?F000:0950 0FB6D8 MOVZX BX,AL - A4 t, v# s+ s! r" g' t
& o; H3 W" B% m3 lInstruction for CPU step 38
& A! V8 ~. R6 |( |5 lF000:0953 6633C0 XOR EAX,EAX
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' f% k' T0 S% G; K0 }/ y4 bInstruction for CPU step 39
8 T5 P S: y9 U1 D1 H1 A4 y" k* ZF000:0956 668BD0 MOV EDX,EAX 1 F9 t+ V8 |4 T
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Instruction for CPU step 40+ Y# J+ c# K( B5 B; f. s
F000:0959 B95002 MOV CX,0250 . G2 E2 ?2 }9 d5 ?* f
# g& ]- T& I: k, L1 I0 F% fInstruction for CPU step 41/ T* M4 S8 U! n. ^% q6 P: B3 y3 D
F000:095C 0F30 WRMSR
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Instruction for CPU step 42
$ x" g3 ?+ Y; L6 H' w) ?( HF000:095E B95802 MOV CX,0258 % f, y7 X9 a8 {4 R! m# l
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Instruction for CPU step 43" J% T% {7 h2 S! W
F000:0961 0F30 WRMSR
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. F h3 z1 {3 q) RInstruction for CPU step 448 C! A$ D) P" u9 @/ H$ U
F000:0963 B95902 MOV CX,0259 , P& ^/ \. }* X* Y
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Instruction for CPU step 45
6 q6 A. J, y, [% ?! P6 \ D$ t% zF000:0966 0F30 WRMSR
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Instruction for CPU step 46
: U, R- K/ Q7 T1 W# n, vF000:0968 B96802 MOV CX,0268
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Instruction for CPU step 47" P# L' h- u( M$ x8 R2 l( T
F000:096B 0F30 WRMSR
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Instruction for CPU step 48
( B& L/ F. L' O2 n4 m0 [F000:096D B96902 MOV CX,0269 + `6 U. p) }, p- B f& U
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Instruction for CPU step 49
; K0 U& Z# g; y% ?$ [( A0 HF000:0970 0F30 WRMSR 2 |$ R4 |2 R, u _9 U- N6 w3 x
0 K- V& [* V$ n) ?; N* ZInstruction for CPU step 50
! i) Y- G: v/ V$ S7 [% N/ k6 @F000:0972 B96A02 MOV CX,026a
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Instruction for CPU step 51
( D( @ e" k4 _+ V3 ^0 SF000:0975 0F30 WRMSR 7 y' I6 Q& y" \$ T6 }
( Z$ R. z1 T. o' s BInstruction for CPU step 52
* f. a# ? T A! IF000:0977 B96B02 MOV CX,026b
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Instruction for CPU step 53
3 v( B5 j H6 MF000:097A 0F30 WRMSR : }1 Q; W4 R2 C2 x" a; D5 L! [2 i. {
) Z ]9 t5 m4 D. eInstruction for CPU step 548 H: C# L5 u! M! K: N2 A
F000:097C B96C02 MOV CX,026c
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Instruction for CPU step 553 a7 v5 Q0 T2 j; ~" N% k
F000:097F 0F30 WRMSR 4 f) B" j( F8 g9 c1 @
- ~* E# e+ a. F4 d# xInstruction for CPU step 56, D: l( Q6 }/ i: k
F000:0981 B96D02 MOV CX,026d , M+ ?4 D- W6 D
8 \6 t" e) H+ I, IInstruction for CPU step 57) L/ g& c( A3 @
F000:0984 0F30 WRMSR
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8 f( R5 s* P$ k# J; X8 p8 }Instruction for CPU step 58
2 I$ g$ K: Y0 A4 t7 [5 x+ eF000:0986 B96E02 MOV CX,026e % f) r+ Z/ r+ O
* t# w7 v( M3 }1 M: [Instruction for CPU step 59
6 N2 T" Y' R! [F000:0989 0F30 WRMSR
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0 u( d: {. o+ T- HInstruction for CPU step 600 R% P4 _! l8 }% z1 ?6 F3 }. Y7 G
F000:098B B96F02 MOV CX,026f
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Instruction for CPU step 610 M4 F( P e3 C1 Q8 @+ U V" Y2 t
F000:098E 0F30 WRMSR
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8 k0 O! P' H0 ^. |$ ~Instruction for CPU step 62" v" L7 Y7 F- W3 p3 P% U
F000:0990 D1E3 SAL BX,1
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Instruction for CPU step 63
; J, k6 G+ G" d7 a' VF000:0992 B90002 MOV CX,0200 ( D- P3 Q, ]2 g$ q+ m( F& ]
, [1 A& _4 a0 [) k9 n$ ]7 O. }* @Instruction for CPU step 64
: Y+ Z5 c/ _9 H* @9 r: s1 ~F000:0995 4B DEC BX . S& }: J1 c4 `
# I; W" @# d' ]2 U1 q, yInstruction for CPU step 65
0 l. K6 H7 g; p5 q1 ?F000:0996 0F30 WRMSR
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- h1 S# ?( K1 S( O7 y* Y. FInstruction for CPU step 66. ^2 M1 A9 o' j S
F000:0998 41 INC CX
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6 ~3 [+ A% j; x1 p, I2 v& L& gInstruction for CPU step 673 p4 ^7 G4 {9 y* n
F000:0999 0BDB OR BX,BX
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- o1 {9 [% y" w7 F3 [Instruction for CPU step 68
" Z6 Z& x/ M- {( F2 g. f5 `0 tF000:099B 75F8 JNE short ptr 0995
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6 t1 s- q7 Z0 s/ N; yInstruction for CPU step 69/ [. I% z% c( F/ T* J, h3 e% T* [
F000:0995 4B DEC BX
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Instruction for CPU step 70
1 `+ J0 w; |, j7 @7 [8 l0 |F000:0996 0F30 WRMSR & V s; M* T3 L& r% t+ [0 ]
( }8 @9 s1 O3 o6 C1 WInstruction for CPU step 71
( W* k V2 I/ L1 x; n: YF000:0998 41 INC CX ' l- e' `* A) L+ K. d" Y, o" f
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Instruction for CPU step 723 L, M' {2 S3 @0 u3 a
F000:0999 0BDB OR BX,BX
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" A$ _/ u0 y. a" A& F4 p7 A0 b: F! }- tInstruction for CPU step 73
- p8 [( F3 D! H& d5 h' B/ @1 hF000:099B 75F8 JNE short ptr 09959 U& r2 W; A$ x) e, p$ \8 G- u
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Instruction for CPU step 74
0 m& Z: X( y' m: U3 {F000:0995 4B DEC BX
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Instruction for CPU step 75
' Z7 J6 r+ N" e; m k% zF000:0996 0F30 WRMSR 7 Z+ n" M' |# e) _
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Instruction for CPU step 76& w- J+ ^$ j, C, C
F000:0998 41 INC CX 9 p+ {- N5 `( D) y/ X
# j! n$ B T mInstruction for CPU step 770 F! X! z8 O9 x& k2 g. I
F000:0999 0BDB OR BX,BX
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+ M3 `/ J5 Z& JInstruction for CPU step 78
# o$ w9 d9 p3 B2 M: @, ?' L% lF000:099B 75F8 JNE short ptr 0995! }6 V8 G; a: G* f* ~: }
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Instruction for CPU step 79* s4 t2 z" s9 Q' E1 n
F000:0995 4B DEC BX 3 G3 i s7 X5 J& P0 Z, ^* C
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Instruction for CPU step 80* f, a2 o% Y" z. k( q/ \) f$ Z
F000:0996 0F30 WRMSR
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Instruction for CPU step 81
9 Y/ j, y! Q; F: Y/ yF000:0998 41 INC CX
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Instruction for CPU step 82
% m! r L, s+ n H# W5 m, `/ i, M' s$ UF000:0999 0BDB OR BX,BX $ y+ ]+ D. l2 {/ u1 A# N- ^
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Instruction for CPU step 83: I) a3 y3 H8 t; _- s
F000:099B 75F8 JNE short ptr 0995
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, r" |3 M) y4 Y" ~1 ^7 g4 b6 l1 rInstruction for CPU step 84
5 E) c$ k/ C' b7 f6 u7 F( ^& XF000:0995 4B DEC BX
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Instruction for CPU step 85, y0 `: h9 x% f" S- v: H( d
F000:0996 0F30 WRMSR $ A! B5 T9 X& ~- D3 [6 {
! `* n( Y z' U0 g3 |6 U4 O0 z vInstruction for CPU step 86$ O+ w7 N" c l: I% W
F000:0998 41 INC CX 2 h. _" Q1 a6 E
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Instruction for CPU step 87; s6 z/ {, m5 V; |
F000:0999 0BDB OR BX,BX
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Instruction for CPU step 88/ n9 q" ?9 ]+ G1 \+ g
F000:099B 75F8 JNE short ptr 0995
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Instruction for CPU step 89
& Q, ]: K d# N* e* ]F000:0995 4B DEC BX
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8 u# _1 z; O, o3 c& rInstruction for CPU step 90, D: ? u- W& | [0 }
F000:0996 0F30 WRMSR
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% F4 I: i' f7 H% ?4 M2 \Instruction for CPU step 91
8 N+ A1 c6 \: ~2 gF000:0998 41 INC CX 1 P5 F9 p: D& H' |( g7 T
$ @8 l2 U+ W" [2 c( wInstruction for CPU step 92* L! ]* B, Y; ?" }% Z
F000:0999 0BDB OR BX,BX
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' Q1 Q8 \$ \( q) E6 l. M; c) @* ZInstruction for CPU step 93, V# p2 w i1 e. _5 h
F000:099B 75F8 JNE short ptr 0995
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Instruction for CPU step 942 |4 O/ X5 ]' m) a0 M) K
F000:0995 4B DEC BX
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$ z- b0 i- I3 [5 Q- P1 Y+ J1 A. b* o& dInstruction for CPU step 95
, [7 l" r5 @+ l u% D dF000:0996 0F30 WRMSR
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Instruction for CPU step 96
G4 H0 Q, V6 G4 Z7 }5 fF000:0998 41 INC CX
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Instruction for CPU step 97, x: O( G6 t, b' i* X( w- z% i
F000:0999 0BDB OR BX,BX
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) X/ J+ `" c( TInstruction for CPU step 988 \3 e4 g" N( C
F000:099B 75F8 JNE short ptr 0995
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Instruction for CPU step 99+ l: }$ u& T! A. J# m
F000:0995 4B DEC BX
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1 ]5 l* J ~2 t5 Z' `: L2 Y1 PInstruction for CPU step 100' R8 v/ F5 c/ J- m! \+ g! |& F/ n
F000:0996 0F30 WRMSR
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* G9 m# @! K: F( X3 DInstruction for CPU step 101
) V2 m0 W: m0 J U/ t/ C$ _F000:0998 41 INC CX ) E! @$ k6 w9 x9 R$ b
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Instruction for CPU step 102
2 u3 y6 u U; ]7 R" ~9 \. ~F000:0999 0BDB OR BX,BX
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0 m. G t% d3 t7 N) B FInstruction for CPU step 103
0 _# {7 Z1 p6 L- b; D }F000:099B 75F8 JNE short ptr 0995
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Instruction for CPU step 104
" u m9 Q6 }' w0 B" e9 H( n3 tF000:0995 4B DEC BX |
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