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PIC 、APIC(IOAPIC LAPIC)

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发表于 2010-10-29 16:11:58 | 显示全部楼层 |阅读模式
PIC APIC(IOAPIC LAPIC)
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1. Overview
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6 P) Q) U: ?5 L; |9 aPIC全称Programmable Interrupt Controller,通常是指Intel 8259A双片级联构成的最多支持15interrupts的中断控制系统。APIC全称Advanced Programmable Interrupt ControllerAPIC是为了多核平台而设计的。它由两个部分组成IOAPICLAPIC,其中IOAPIC通常位于南桥中1 e- F7 U$ X# c8 Z/ n+ O& Q
用于处理桥上的设备所产生的各种中断,LAPIC则是每个CPU都会有一个。IOAPIC通过APICBUS(现在都是通过FSB/QPI)将中断信息分派给每颗CPULAPIC,CPU上的LAPIC能够智能的决定是否接受系统总线上传递过来的中断信息,而且它还可以处理Local端中断的pendingnestingmasking,以及IOAPICLocal CPU的交互处理。; O0 k9 f4 g' B7 o1 a, z  O

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( P( f( x$ i8 }) Z2. PIC3 s/ o# i8 Q/ j* ^+ U

4 s5 S% ~: p6 m: k基于Intel 80x86PC使用两片8259A级联的方式组成了可以管理15级中断向量的一个中断系统,下图是它的一个连接示意图。两片8259A,一片为Master,另一片为Slaver。其中SlaverINT接到MasterIRQ2上。8259A有两种工作模式分别为编程和操作模式。BIOS初始化的时候会先通过IO port8259A进行编程配置,在此之后8259A就可以响应来自外部设备的中断请求了。MasterIO address0x20 0x21; SlaverIO address0xA0 0xA1
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; W/ V: `0 `3 f' D PIC.jpg ! h( Y! b- Q0 Q! I/ a" V; F

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为了能够正常的使用PIC来管理系统中断,就需要对它进行初始化。8259A支持两种类型的命令字,一类是初始化命令字ICW1~4,另一类是操作命令字OCW1~3,其中每一个命令字的各个bit都有其代表的特定意义。下述是一个初始化Master的一个sample code" W9 T4 u5 m5 {$ a

+ D) c. Z- V& N9 {& c+ C& IMOV
; \5 G( m' r- ~1 J# @: tAL,00010001b( c+ R' _8 b2 Q6 I  J6 H9 _
;级联,边沿触发,需要写ICW4% Y2 e! N* S7 j
OUT/ o2 s/ A9 z3 o7 i7 I* s
20H,AL
. y/ r' c2 y1 A3 v1 z* Z;ICW1
2 y1 N- K8 M  E( hMOV! b# A  a/ C2 t
AL,01000000B ;中断类型号40H) z$ U, n' Y8 T" R/ w2 `( r! E  U
OUT, H  _# f& _& g' S
21H,AL2 Q; C% A+ _0 z
;ICW2
" }, _& o4 i: V$ D0 i) @; ~MOV
5 R/ Z2 _5 @' X! F2 G$ P0 D" XAL,00000100B;主片的IR2引脚从片
- |# S% Y. o$ |1 TOUT
. m, o0 l8 ]7 B+ u! x' j: N21H,AL
, W3 m( t% r  L;ICW3
* n% k( J2 N9 S0 X2 z: {MOV
4 ?1 \$ b% W2 Y+ d/ l8 ~- Q5 ~AL,00010001B;特殊完全嵌套,非缓冲,自动结束$ `# [$ b0 d- y5 o
OUT
: o( |9 H# N9 l( v) K7 I3 h21H,AL
% S$ y2 Z8 L" t;ICW4
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3. APIC! X% C& k8 a8 ^& H
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Intel APIC由一组中断输入信号,一个24*64bitProgrammable Redirection Table(PRT),一组register和用于从APIC BUS(FSB/QPI)上传送APIC MSG的部件组成,当南桥的IO device通过IOAPICinterrupt lines产生interruptIOAPIC将根据内部的PRT table格式化成中断请求信息,并将该信息发送给目标CPULAPIC,再由LAPIC通知CPU进行处理。下图是一个基于Intel APIC的连接示意图,如下图所示IOAPIC上有24interrupt pin4 S4 k, y$ Z4 }5 k
每一个pin都对应一个RTE,所以针对每一个interrupt pin都可以单独设定它的mask,触发方式(level,edge trigger),中断管脚的极性,传送方式,传送状态,目的地,中断向量等。
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Programmable Redirection Table详细格式如下所示:
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Bit Description:& r: E0 g$ a( i/ o) d% W! B; `/ m' {2 |
[63:56] Destination Field—R/W.
# f( C0 G( h; I- A  lIf the Destination Mode of this entry is Physical Mode (bit 11=0), bits

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[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field
# W, F- b; B# B3 S3 zpotentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical6 ]' X8 [, x  N$ V) T% m- ]+ b
destination address.
5 K8 U. a2 d0 h% GDestination Mode IOREDTBLx[11] Logical Destination Address8 n9 l) M9 ]9 Q) P& {+ P
0, Physical Mode IOREDTBLx[59:56] = APIC ID
  A4 z* i3 Z- R; n1, Logical Mode IOREDTBLx[63:56] = Set of processors
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[55:17] Reserved.82093AA (IOAPIC) 5 U2 ], A, k, {
[16]# r. N1 |+ o' ]3 R4 J/ i
Interrupt Mask—R/W.* ?# ?+ M9 [! b+ ~  g' D
When this bit is 1, the interrupt signal is masked. Edge-sensitive

" _2 g8 v8 |, ^9 v  w+ J% pinterrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending)./ _$ q9 a+ z& i# o4 _- `3 L1 [
Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no
; N% Y2 @  U- wside effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by
2 }+ |' n& R2 r5 x0 y" Wa local APIC has no effect on that interrupt. This behavior is identical to the case where the2 s" N0 b+ U# U. A' ~4 s2 K& M0 z
device withdraws the interrupt before that interrupt is posted to the processor. It is software's! w  @% ?5 t5 v  z  u8 e
responsibility to handle the case where the mask bit is set after the interrupt message has been
$ _" `0 |% {. R; Z% taccepted by a local APIC unit but before the interrupt is dispensed to the processor. When this1 W) W& s& X5 n
bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked2 e! t% z3 F# K: B$ I* f
results in the delivery of the interrupt to the destination.% v% v& A& g0 M9 Z% y1 u: X
[15] Trigger Mode—R/W.* U( o$ \% Y: q
The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.

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[14] Remote IRR—RO.
/ J9 n9 t' L+ q* w& u. WThis bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC.
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[13] Interrupt Input Pin Polarity (INTPOL)—R/W.
' v8 T* V  U/ Q- I! u3 ?  wThis bit specifies the polarity of the interrupt

6 O/ o/ u! B2 zsignal. 0=High active, 1=Low active.
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[12]$ \. c3 F- e8 l  C, T) h2 l
Delivery Status (DELIVS)—RO.
5 T0 n. j0 ]: d. q! I; A7 `* w" C( {The Delivery Status bit contains the current status of the
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delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit
; V' N( m7 U' Q# @word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send
% h* B' }) p  k. |+ \& X# N9 ?Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC
% S( |& W1 G: U1 y+ Y( ]bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).5 e8 G$ G3 a+ F3 Y
[11] Destination Mode (DESTMOD)—R/W.- D7 N) h" Y8 M$ q4 P* e  }/ w
This field determines the interpretation of the

. m6 U4 b: n) e. [) sDestination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.
: e8 w# n/ y( k* m, K1 pBits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.$ W1 L. z# d- N! e+ A" e
Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)
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[10:8]Delivery Mode (DELMOD)—R/W.2 p5 [1 T) @. P/ R
The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain

' ]5 _" v% |  R8 e2 b& FDelivery Modes only operate as intended when used in conjunction with a specific trigger Mode.
0 ?) k3 b( P4 w& b. U; W. bThese restrictions are indicated in the following table for each Delivery Mode.
2 B4 P3 i9 q* n2 X, U, |Mode Description
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Fixed Deliver the signal on the INTR signal of all processor cores listed in the

& G- J% c9 f5 X8 Bdestination. Trigger Mode for "fixed" Delivery Mode can be edge or level.
6 K& f" L$ _" d3 Q$ o4 }( G001
$ Z) V+ b8 n" |, s# cLowest
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Priority Deliver the signal on the INTR signal of the processor core that is. W# I  x: n+ b8 Q( d$ ]0 Q
executing at the lowest priority among all the processors listed in the
2 m; @$ A  M- b0 l3 I/ m+ `specified destination. Trigger Mode for "lowest priority". Delivery Mode
1 m0 p4 r0 h0 G1 bcan be edge or level.( S$ e6 M5 {! E
010
, R; i; U! o  R' R1 u7 _  @SMI System Management Interrupt. A delivery mode equal to SMI requires an

* Z' ?, p# O  W9 c3 U( ~edge trigger mode. The vector information is ignored but must be  {4 X  k* }' S4 D/ E
programmed to all zeroes for future compatibility.- i4 E; T8 f0 [! q# b7 i
011
, T; S* e- v) ?1 _Reserved

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NMI Deliver the signal on the NMI signal of all processor cores listed in the

9 p4 u* T/ Z4 S! Q$ vdestination. Vector information is ignored. NMI is treated as an edge
) A3 z' a6 B* b# O' itriggered interrupt, even if it is programmed as a level triggered interrupt.
/ o$ T7 `; y' f& W: {6 |For proper operation, this redirection table entry must be programmed to0 A0 E5 U9 ?$ `$ ?8 g, C" r
edge” triggered interrupt.0 j* I0 a6 d% l. i: E& i- Q
101
* n; p+ j8 `  X# E) \4 V; z$ \INIT Deliver the signal to all processor cores listed in the destination by

/ d5 _/ b- ^- v" Gasserting the INIT signal. All addressed local APICs will assume their
- |3 i6 u* _, W  S7 zINIT state. INIT is always treated as an edge triggered interrupt, even if
2 M; `9 ~6 j' k8 e1 ^programmed otherwise. For proper operation, this redirection table entry
8 g% h& U) m2 U5 i0 xmust be programmed to “edge” triggered interrupt.& m: D6 ?6 M5 T1 q+ [& x* Z( E$ O- T
1104 T& ?& M8 H# [  v7 R7 o
Reserved
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1118 ^, K8 t) }" ~% N
ExtINT Deliver the signal to the INTR signal of all processor cores listed in the

+ }) P) [6 r7 @9 N4 odestination as an interrupt that originated in an externally connected5 P$ I) h2 F9 V( F. B  n' {
(8259A-compatible) interrupt controller. The INTA cycle that corresponds, Z. c, I  R/ @1 O% \2 O) Z' U
to this ExtINT delivery is routed to the external controller that is expected- L$ w  P) c- M' O0 U
to supply the vector. A Delivery Mode of "ExtINT"
- {+ Z' V0 n  |  w" Xrequires an edge
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trigger mode.% v' _- q6 P# O# e& z, d
[7:0] Interrupt Vector (INTVEC)—R/W:
  g+ J9 x/ Y; h% N" x: M% m( ^The vector field is an 8 bit field containing the interrupt

( h* }7 S1 i9 {/ I# D* lvector for this interrupt. Vector values range from 10h to FEh.9 j5 v* u) v% T/ \" F
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REFF:8 g* O; s" d7 R- H% @2 E# r
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1.
3 i: G( E6 o) h82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)
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8 Q* ~6 K6 f/ @6 y8259A PROGRAMMABLE INTERRUPT CONTROLLER(8259A/8259A-2): M( r, H- Q" O9 G( A. u
3.
  r' ?7 I& z" f( T9 o5 uUndocumented PC. `, z. z2 D* C4 c
4.
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8259A初始化编程! T% e7 H8 m0 d: F1 m- A( F" a. q( _
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That’s all!$ T/ j6 j* z% i. j- k( Z( L
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Peter8 V+ D# S6 v5 h8 V( D+ w
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2010/10/07  k' Q  b; b+ d+ Z% t1 |) ?. J0 f
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[ 本帖最后由 peterhu 于 2010-10-29 16:13 编辑 ]
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