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PIC 、APIC(IOAPIC LAPIC)

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发表于 2010-10-29 16:11:58 | 显示全部楼层 |阅读模式
PIC APIC(IOAPIC LAPIC)

) ]6 l* _8 D" q! ]- O1. Overview
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PIC全称Programmable Interrupt Controller,通常是指Intel 8259A双片级联构成的最多支持15interrupts的中断控制系统。APIC全称Advanced Programmable Interrupt ControllerAPIC是为了多核平台而设计的。它由两个部分组成IOAPICLAPIC,其中IOAPIC通常位于南桥中( \& T% E; g( I
用于处理桥上的设备所产生的各种中断,LAPIC则是每个CPU都会有一个。IOAPIC通过APICBUS(现在都是通过FSB/QPI)将中断信息分派给每颗CPULAPIC,CPU上的LAPIC能够智能的决定是否接受系统总线上传递过来的中断信息,而且它还可以处理Local端中断的pendingnestingmasking,以及IOAPICLocal CPU的交互处理。3 @1 Q4 y! m% e" C# O
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, P( r; h) Z1 n4 g1 [* b' N% Y6 w2. PIC( W  S$ J& H+ V% k) |
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基于Intel 80x86PC使用两片8259A级联的方式组成了可以管理15级中断向量的一个中断系统,下图是它的一个连接示意图。两片8259A,一片为Master,另一片为Slaver。其中SlaverINT接到MasterIRQ2上。8259A有两种工作模式分别为编程和操作模式。BIOS初始化的时候会先通过IO port8259A进行编程配置,在此之后8259A就可以响应来自外部设备的中断请求了。MasterIO address0x20 0x21; SlaverIO address0xA0 0xA1( n/ a- i; D- Y' h) I) X. G2 U+ ?
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PIC.jpg
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4 d4 D" a. I8 J5 x, W为了能够正常的使用PIC来管理系统中断,就需要对它进行初始化。8259A支持两种类型的命令字,一类是初始化命令字ICW1~4,另一类是操作命令字OCW1~3,其中每一个命令字的各个bit都有其代表的特定意义。下述是一个初始化Master的一个sample code
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% ]5 o* |. ?: \& c" }# \MOV3 ~+ }$ I/ Y9 x) o3 T& ]
AL,00010001b
, G+ |+ ?+ A2 w" f6 ^! m+ G;级联,边沿触发,需要写ICW42 `4 m9 ~, W& I# H
OUT% l- J# Y$ B  e4 ]9 }" E
20H,AL& ~0 Q4 s9 ?3 }* l0 c, Y" C& m" d
;ICW1) ]8 L5 H% @, y9 F, o$ l
MOV  o. }2 y" H" J
AL,01000000B ;中断类型号40H
, V; m* h/ s7 Q/ f1 ^2 O- Q0 Q/ HOUT
' e) i. b! P$ r* M. U, A+ z! y/ a21H,AL. t! i8 g* _, K% p  j
;ICW2
  b; p, _& \' c0 _5 QMOV
: F5 s& A4 e* ?AL,00000100B;主片的IR2引脚从片3 U+ j0 I1 c. f  I- o
OUT
# q0 `4 f8 z: B; O# C& o. m21H,AL
; H! c1 P& Y& t0 g3 F$ [0 ~8 G;ICW3* i0 ]( b6 I+ i# B9 q- I1 v  I0 Q
MOV: E) I1 A; x0 S* t/ O- o- M* d
AL,00010001B;特殊完全嵌套,非缓冲,自动结束
% l, w+ p8 z- \% a3 p7 P. tOUT, a; d2 P+ [+ [5 Q: r" m/ O$ x/ c
21H,AL3 \7 P5 p  q  j9 L
;ICW49 q) X) V, [  K) {( h0 [3 s
8 }2 N2 V, ?3 `
3. APIC6 ]; Q# @) j! O) e, c

' i& l% f- w2 w* S( y1 P  kIntel APIC由一组中断输入信号,一个24*64bitProgrammable Redirection Table(PRT),一组register和用于从APIC BUS(FSB/QPI)上传送APIC MSG的部件组成,当南桥的IO device通过IOAPICinterrupt lines产生interruptIOAPIC将根据内部的PRT table格式化成中断请求信息,并将该信息发送给目标CPULAPIC,再由LAPIC通知CPU进行处理。下图是一个基于Intel APIC的连接示意图,如下图所示IOAPIC上有24interrupt pin
  x4 |7 @# |. R' U* s每一个pin都对应一个RTE,所以针对每一个interrupt pin都可以单独设定它的mask,触发方式(level,edge trigger),中断管脚的极性,传送方式,传送状态,目的地,中断向量等。
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IOAPIC.jpg
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+ l% C! T) o# V1 U) _4 u: VProgrammable Redirection Table详细格式如下所示:
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Bit Description:
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[63:56] Destination Field—R/W.
9 E+ }( j: k# [: W- a- A0 O8 U& xIf the Destination Mode of this entry is Physical Mode (bit 11=0), bits

2 {( G" H$ P! K( @6 X
[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field
. m- U+ v# |' E8 k. L5 T) y6 U( hpotentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical& _. @" Q2 y! b5 R- }
destination address.
& M! d! W! N3 `0 A$ W* ]Destination Mode IOREDTBLx[11] Logical Destination Address$ O) n( t$ A2 w) k7 @3 `- Z
0, Physical Mode IOREDTBLx[59:56] = APIC ID0 e4 u6 m' \; n
1, Logical Mode IOREDTBLx[63:56] = Set of processors
5 h1 r9 m. E/ b' a
[55:17] Reserved.82093AA (IOAPIC)
# X. \: F3 n. X, D# K' R
[16]5 x; ]  Z/ n  H6 I3 C' X( \6 D
Interrupt Mask—R/W.
! O8 c5 R! o, C9 u! \/ `When this bit is 1, the interrupt signal is masked. Edge-sensitive
% r; _' I* K$ L  x* Z0 w7 i- X+ r
interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending).0 R5 g0 [3 z9 }7 q! @
Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no. x) ]. L. X0 F0 ?, ]. m9 {1 }
side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by4 B. l9 a% |+ T8 M/ I9 m
a local APIC has no effect on that interrupt. This behavior is identical to the case where the- e0 H9 ~8 V( k7 z5 T0 E9 M1 C
device withdraws the interrupt before that interrupt is posted to the processor. It is software's+ W- X. u! i. S& K' F3 ^9 A" t  b7 Z
responsibility to handle the case where the mask bit is set after the interrupt message has been
3 M8 k; E2 q! S9 F' U# ]) I* Paccepted by a local APIC unit but before the interrupt is dispensed to the processor. When this' c& D* R# i/ x! V6 p; x
bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked, P' x$ t# p) t* R+ |) d9 D8 A' \
results in the delivery of the interrupt to the destination.; g& m( y) {, h$ ]. W
[15] Trigger Mode—R/W.1 O7 K8 ]4 O% K9 t$ `. j# g! U0 Q: m) d
The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.

9 O  K  c/ W& L
[14] Remote IRR—RO.0 n( i6 }: f0 I8 W
This bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC.

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[13] Interrupt Input Pin Polarity (INTPOL)—R/W.
( M( ?$ t' Q: H/ B: |8 KThis bit specifies the polarity of the interrupt

& E7 \. h" ]- _$ rsignal. 0=High active, 1=Low active.* @5 y# q: H3 I4 E  u$ e  b
[12]
& e+ C4 h3 C1 oDelivery Status (DELIVS)—RO., P  Y5 s# h$ r' P: E6 D2 ^4 q
The Delivery Status bit contains the current status of the

0 `( K5 V  z, W. w, \4 j1 ^  Xdelivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit
2 X- X8 H: x: t; }% eword) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send
$ s+ A1 g. w0 `0 r# ~+ F+ DPending (the interrupt has been injected but its delivery is temporarily held up due to the APIC
; m2 z8 M2 m6 W, O, L+ pbus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).
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[11] Destination Mode (DESTMOD)—R/W.5 C5 ]4 U/ S2 X3 D0 ]5 l
This field determines the interpretation of the

! Z3 P( H  P) V- }! WDestination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.; w) j. V* s% H# d6 B
Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.3 y, x; G) t. k- ]& Q
Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)
. P3 S4 }/ C; ^7 g
[10:8]Delivery Mode (DELMOD)—R/W.( l& X. E+ |& R1 _) o3 P* n( V
The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain

6 f5 f' L/ q- HDelivery Modes only operate as intended when used in conjunction with a specific trigger Mode.4 B1 ]$ c; j' g3 v
These restrictions are indicated in the following table for each Delivery Mode.5 o( N- Z+ z5 G1 G; l
Mode Description" ~9 x  p/ Y; }
000
2 G" T2 B! f- B3 q$ rFixed Deliver the signal on the INTR signal of all processor cores listed in the
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destination. Trigger Mode for "fixed" Delivery Mode can be edge or level.* m; L7 }5 ]& \4 b. ]6 h
001/ I9 P1 p1 E8 m) [& l: C. H- ^/ z( t/ D
Lowest

2 Q9 |0 l8 ]- b' Z, fPriority Deliver the signal on the INTR signal of the processor core that is' R( K, ^% L% k! x$ x: M8 K
executing at the lowest priority among all the processors listed in the7 y8 K7 f! R! ?4 T
specified destination. Trigger Mode for "lowest priority". Delivery Mode* ~, q: L" n4 V7 }: u3 X
can be edge or level.
1 Z) D  n! m; I/ Y3 [; M010
, Y: X2 p8 C" O9 I! S2 d. lSMI System Management Interrupt. A delivery mode equal to SMI requires an

0 h4 S5 n! C" m3 k1 u( bedge trigger mode. The vector information is ignored but must be
2 B; d8 v5 L# K& aprogrammed to all zeroes for future compatibility.2 L# w5 i0 u# N! ^8 D
011" l1 }7 V! s5 S6 E# e( M# t
Reserved

( ]6 d! u8 P# p3 E+ z( V7 d6 U/ ^100
9 y- ], E( W6 B8 j" G5 |NMI Deliver the signal on the NMI signal of all processor cores listed in the

" ]' M# }) p- K( w2 Ldestination. Vector information is ignored. NMI is treated as an edge
3 L) J2 J" m9 f4 P: A' gtriggered interrupt, even if it is programmed as a level triggered interrupt.: G( @3 i" i: s
For proper operation, this redirection table entry must be programmed to. x; A  m1 r6 I1 U7 f
edge” triggered interrupt.) ?* C9 I1 m9 j" {6 ]
101* N! k7 ]: {+ c4 c. Y, G
INIT Deliver the signal to all processor cores listed in the destination by
# u* v2 W  K6 y; L" W% Z7 q
asserting the INIT signal. All addressed local APICs will assume their& U; z4 `" d* Q4 B( s% r8 D
INIT state. INIT is always treated as an edge triggered interrupt, even if! y2 V  M; u. [1 \
programmed otherwise. For proper operation, this redirection table entry7 g( W/ Q6 i- X2 H
must be programmed to “edge” triggered interrupt.
& a6 H4 a. S4 S$ l! W110
; f. [+ t" a/ j3 g' i7 k8 ^% eReserved
& m, r4 I7 |/ O* I% \3 F/ c% }) C
111
8 L& H5 J& C+ P6 B; LExtINT Deliver the signal to the INTR signal of all processor cores listed in the

0 M+ Y/ K8 L6 c6 k6 E) |$ Ndestination as an interrupt that originated in an externally connected+ u  M) U1 f" M! |' {3 ^$ T, X+ I
(8259A-compatible) interrupt controller. The INTA cycle that corresponds/ a* _/ A8 x1 B5 i( t$ r1 a
to this ExtINT delivery is routed to the external controller that is expected
( [0 h3 {5 j. @! j9 y7 s! cto supply the vector. A Delivery Mode of "ExtINT"
4 P6 B7 J( B" H4 o8 d) nrequires an edge

- e; x4 A0 V2 _! E; s" r5 Itrigger mode.- J8 ]8 e! c5 E, C8 E  V; _
[7:0] Interrupt Vector (INTVEC)—R/W:
& y2 k/ Z) S5 E2 P0 `0 ^The vector field is an 8 bit field containing the interrupt
! n: }. |7 _; r6 p
vector for this interrupt. Vector values range from 10h to FEh., y; E) J' Q2 f" b
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REFF:% a* i4 N" H5 Y" w

. M/ Z, p9 J% y: t/ X2 ^1.! }( I! O+ ]5 y2 M4 Y! j
82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)6 S1 E* n4 O7 S; a. A$ Q( t& f
2.+ G4 o( W9 I% X( e0 }: l
8259A PROGRAMMABLE INTERRUPT CONTROLLER(8259A/8259A-2)
3 S" p+ g( g$ X' n1 D. d  Z3./ v6 W1 K8 H. w* D) p/ m9 ]- w% N
Undocumented PC
+ n4 Q0 T9 t; ~( [! S6 Y' q/ |4.' e9 q! f3 `" I1 A2 i, O

; h7 L7 g. m3 A: `; ?8259A初始化编程
; n; F1 ~5 B: L# \+ ]$ x
0 G- s6 y# z: NThat’s all!" w4 u2 W& Y! }
1 g' k2 E5 w6 _9 D( f) n! N
Peter
( n% y3 w1 `0 Q' j3 q% ~8 H* Z1 b
2010/10/07
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, k6 ?7 w. ]3 p3 b3 N) l[ 本帖最后由 peterhu 于 2010-10-29 16:13 编辑 ]
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