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PIC 、APIC(IOAPIC LAPIC)
& H% [- O: {8 k1. Overview
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, ^- J- t# q4 H7 mPIC全称Programmable Interrupt Controller,通常是指Intel 8259A双片级联构成的最多支持15个interrupts的中断控制系统。APIC全称Advanced Programmable Interrupt Controller,APIC是为了多核平台而设计的。它由两个部分组成IOAPIC和LAPIC,其中IOAPIC通常位于南桥中( t1 ?: c; {! n, |& x' X
用于处理桥上的设备所产生的各种中断,LAPIC则是每个CPU都会有一个。IOAPIC通过APICBUS(现在都是通过FSB/QPI)将中断信息分派给每颗CPU的LAPIC,CPU上的LAPIC能够智能的决定是否接受系统总线上传递过来的中断信息,而且它还可以处理Local端中断的pending、nesting、masking,以及IOAPIC于Local CPU的交互处理。# _) w- L' L4 s- o( `0 A) h' q7 q1 h
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6 Z; }/ F3 d. F) M8 C% X2. PIC
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基于Intel 80x86的PC使用两片8259A级联的方式组成了可以管理15级中断向量的一个中断系统,下图是它的一个连接示意图。两片8259A,一片为Master,另一片为Slaver。其中Slaver的INT接到Master的IRQ2上。8259A有两种工作模式分别为编程和操作模式。BIOS初始化的时候会先通过IO port对8259A进行编程配置,在此之后8259A就可以响应来自外部设备的中断请求了。Master的IO address是0x20 0x21; Slaver的IO address是0xA0 0xA1。( u" x/ u! G* W
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5 x9 Q: m4 S' w/ d+ D' S/ s O为了能够正常的使用PIC来管理系统中断,就需要对它进行初始化。8259A支持两种类型的命令字,一类是初始化命令字ICW1~4,另一类是操作命令字OCW1~3,其中每一个命令字的各个bit都有其代表的特定意义。下述是一个初始化Master的一个sample code:. u4 j' `( t# k5 {7 x4 A
5 H2 e) K* V+ k$ q. \+ GMOV
- R5 [( C3 H' n! z* VAL,00010001b
- f( p" n, @ U3 Z5 ^) q;级联,边沿触发,需要写ICW41 N8 k% L2 V& X1 t% R# f8 a [
OUT
# X% H0 S6 z9 h3 g4 d2 L& S, W, x20H,AL
7 W; h% m, k. c;写ICW1
% w, @, e! w- n$ s$ MMOV
( H) h& w; y! v2 b- yAL,01000000B ;中断类型号40H: w5 @' E( i7 y' u/ e7 R4 k5 k
OUT% @* a5 s" a7 R1 S
21H,AL
2 P- P" J+ w* z;写ICW2
: c2 p& n8 u' h/ xMOV) O) h- `% g+ N& x3 w' V
AL,00000100B;主片的IR2引脚从片
, t9 E F1 j F- DOUT
4 q8 a; F1 [5 L r$ u9 }2 q. ^21H,AL) [1 Z; D5 v, d( S
;写ICW32 e3 n* m3 F0 q) ?# Y. n
MOV
7 R7 ]- A5 N2 w0 t) X# i& q" dAL,00010001B;特殊完全嵌套,非缓冲,自动结束) s$ p3 |3 t8 M5 t
OUT7 v' T, F `" ~ y
21H,AL
. p K! N+ r) o1 ]4 k8 }: s;写ICW4
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/ z8 z8 ~& l( f: c3. APIC! F; I6 X7 Y s( p- f' ~6 c: m0 T" ?
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Intel APIC由一组中断输入信号,一个24*64bit的Programmable Redirection Table(PRT),一组register和用于从APIC BUS(FSB/QPI)上传送APIC MSG的部件组成,当南桥的IO device通过IOAPIC的interrupt lines产生interrupt,IOAPIC将根据内部的PRT table格式化成中断请求信息,并将该信息发送给目标CPU的LAPIC,再由LAPIC通知CPU进行处理。下图是一个基于Intel APIC的连接示意图,如下图所示IOAPIC上有24个interrupt pin,
) x8 a# U9 K+ J' K7 B每一个pin都对应一个RTE,所以针对每一个interrupt pin都可以单独设定它的mask,触发方式(level,edge trigger),中断管脚的极性,传送方式,传送状态,目的地,中断向量等。: w; X6 Z& B6 `4 h# K
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Programmable Redirection Table详细格式如下所示:
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Bit Description:
% M/ v q" ]% X; a | [63:56] Destination Field—R/W.$ c, @( o* d& W: \2 J
If the Destination Mode of this entry is Physical Mode (bit 11=0), bits
2 J6 S9 \8 W7 Z3 s1 R | [59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field' F7 A3 M9 _! q
potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical
3 w5 M: e* M1 m7 mdestination address.
+ H7 J5 [; q! fDestination Mode IOREDTBLx[11] Logical Destination Address( t3 M% U* h) [/ c' ^: S
0, Physical Mode IOREDTBLx[59:56] = APIC ID- W) _) e D+ T* D# u0 w9 P6 d( k
1, Logical Mode IOREDTBLx[63:56] = Set of processors; k1 t" l+ C% A1 Z( l
| [55:17] Reserved.82093AA (IOAPIC)
. ?& w6 _; a3 J4 _! N" R4 e | [16]. Z; j3 }" U! Z. P* {7 m
Interrupt Mask—R/W.
8 a) d% O: [0 v$ ?When this bit is 1, the interrupt signal is masked. Edge-sensitive
! S, ~+ j7 V! n: y; I7 Jinterrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending).3 _- ^ z0 g0 N" I
Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no
& u9 }6 W# y/ x9 m1 e& {side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by
; c4 L0 d8 D" K7 d/ Ga local APIC has no effect on that interrupt. This behavior is identical to the case where the3 @" U/ C! @5 u
device withdraws the interrupt before that interrupt is posted to the processor. It is software's
+ x! \% j, g! K2 Z# mresponsibility to handle the case where the mask bit is set after the interrupt message has been
0 ]6 K1 e6 D# j: _2 B& \ Y& k! caccepted by a local APIC unit but before the interrupt is dispensed to the processor. When this
d8 |! D( {( v. W1 m3 ~' N+ gbit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked
+ |) |3 @$ W4 y( Y: \3 Yresults in the delivery of the interrupt to the destination.
/ I1 m0 K9 s4 @ | [15] Trigger Mode—R/W.1 S, @! W0 p3 a1 S
The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.
& Q# v+ D$ R. M6 x! [1 ^3 j+ S- x. m; r | [14] Remote IRR—RO.
% u4 O" f2 ]; w8 x; G- w: gThis bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC.
8 Y2 s' H0 c! I | [13] Interrupt Input Pin Polarity (INTPOL)—R/W.
6 Y5 o& K& A1 _) ~7 S+ PThis bit specifies the polarity of the interrupt* e- [) Y' Z7 n& w. |
signal. 0=High active, 1=Low active.
$ h) j& i+ j: N# U4 w! r" m( { | [12]! k7 t. Q5 c3 ?5 h
Delivery Status (DELIVS)—RO.: L( Y, D0 I) m/ ]. w+ j( v
The Delivery Status bit contains the current status of the$ V% c( c9 _! {7 r, @
delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit
& J; o6 T" y' t& [' }word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send8 b9 C- r5 w( g5 H! p
Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC( ]5 R- g; q/ m0 [9 y6 P
bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).
6 Z c9 J: {7 ^, X' Y | [11] Destination Mode (DESTMOD)—R/W.
- I' x0 }6 G2 v" T) hThis field determines the interpretation of the
1 }; G1 n; [- D9 ^) p+ YDestination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.. z& Q" \0 y& q6 ~* t! t
Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.8 t6 `/ Y4 J" @* ?
Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)
& {# K1 c+ S* A | [10:8]Delivery Mode (DELMOD)—R/W.( e+ b3 r" r4 b3 n4 F. I [6 F
The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain# _& M C( r7 v0 l3 J4 s
Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode.
6 J8 y% H: q5 e* RThese restrictions are indicated in the following table for each Delivery Mode.
& p% K' s# \; `1 ~$ qMode Description: a+ v. a! V$ @' Q4 y! H* h
000
4 z2 |/ k+ C/ v8 iFixed Deliver the signal on the INTR signal of all processor cores listed in the4 n8 j% P* {' _, O1 {
destination. Trigger Mode for "fixed" Delivery Mode can be edge or level.* X* n3 V- j( h4 d
001
8 k* V0 D* J4 ^8 l9 `4 k' w cLowest
# {$ w8 h; G N& bPriority Deliver the signal on the INTR signal of the processor core that is
) F, C% {+ v0 X7 F/ pexecuting at the lowest priority among all the processors listed in the
* r$ U1 ]- e2 Y0 e+ \1 i+ Hspecified destination. Trigger Mode for "lowest priority". Delivery Mode
N; l7 c" G' L$ Z. \can be edge or level.. S5 V7 S2 e# N3 }4 Y
0107 v+ v- g e2 j+ d( [* Y
SMI System Management Interrupt. A delivery mode equal to SMI requires an0 V7 F4 V5 |7 Y" F" ~+ j! l
edge trigger mode. The vector information is ignored but must be
9 Y, l# t! S8 T! D* Eprogrammed to all zeroes for future compatibility.1 b8 V" O* E" H
011
! y0 A" W {0 P6 E# n( `( W' ]9 gReserved
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NMI Deliver the signal on the NMI signal of all processor cores listed in the
1 q8 J$ d( V/ n; Y: edestination. Vector information is ignored. NMI is treated as an edge2 i( r+ G/ E5 S" N8 @8 Z
triggered interrupt, even if it is programmed as a level triggered interrupt.
) k- s1 c- C, aFor proper operation, this redirection table entry must be programmed to) W+ ^% _: \* E# Q0 t5 F" w2 S
“edge” triggered interrupt.
+ Y1 q) R% t n5 |: m1 Y _$ X101
2 P9 M$ D& x8 I% W4 TINIT Deliver the signal to all processor cores listed in the destination by4 ~# d( a; ]. \% E1 x& ]! a2 b
asserting the INIT signal. All addressed local APICs will assume their7 E, \- N! ]+ C( s0 w& [% H1 ]
INIT state. INIT is always treated as an edge triggered interrupt, even if
- p, Q' f' U8 i. Kprogrammed otherwise. For proper operation, this redirection table entry% T# j+ E. ?) U8 Q
must be programmed to “edge” triggered interrupt.( ]' ?8 e4 D: J7 I8 ^; x+ Q
110
# K# @5 A0 F6 WReserved5 o3 x. Q! r5 \2 f
111
5 i- z0 k3 I _' O8 u" sExtINT Deliver the signal to the INTR signal of all processor cores listed in the
9 _: D* ]$ ?4 j- j, wdestination as an interrupt that originated in an externally connected! |0 P( _' g: O5 a1 K
(8259A-compatible) interrupt controller. The INTA cycle that corresponds
" A) |4 a. o. u0 hto this ExtINT delivery is routed to the external controller that is expected: v+ f3 J( ^- J* f
to supply the vector. A Delivery Mode of "ExtINT"# }$ e; C+ y; U2 i
requires an edge
% j4 o0 m- C' K: ?& Ktrigger mode.* D' h9 o" c% v4 e7 O" x" }
| [7:0] Interrupt Vector (INTVEC)—R/W:! I7 X/ {$ @' P! r
The vector field is an 8 bit field containing the interrupt7 I- F' g$ c0 M4 S6 L7 V; o: M
vector for this interrupt. Vector values range from 10h to FEh.
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& x7 M; N9 G; Z* @, Y. I; C- ?REFF:- ^8 Y) D% I) N8 P( R* g
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6 R; ?, V! Y9 N1 M- A: J$ [《82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)》5 f$ N) A# Z7 A' }) q
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《8259A PROGRAMMABLE INTERRUPT CONTROLLER(8259A/8259A-2)》
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5 H) k7 O4 D/ {# h( E$ b3 w" a7 l《Undocumented PC》
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0 @' `% w6 @8 B8259A初始化编程
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6 H& g+ R4 i3 r0 G, o5 ~That’s all!$ e7 h" y) W3 M2 G
+ E" {/ z. c- e' nPeter
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2010/10/07
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[ 本帖最后由 peterhu 于 2010-10-29 16:13 编辑 ] |
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