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URL Link: http://www.intel.com/technology/framework/spec.htm0 B }* v9 S# I5 r3 p: t: \
The Intel® Platform Innovation Framework for EFI Architecture Specification describes the primary design elements of an innovative approach to constructing platform firmware for platforms based on Intel® architecture. The design is characterized by a central “framework” that provides services and infrastructure to combine modular software building block elements. Taken together, the infrastructure code—which is known as the Foundations—and an appropriate selection of modular building blocks constitute a complete platform software implementation that is designed to initialize the platform and boot shrink-wrap operating systems or other custom application environments. The Foundations are comprised of the Pre-EFI Initialization (PEI) and Driver Execution Environment (DXE) phases, which are both described in this specification. In addition, this specification describes a number of other design elements in an effort to provide a complete set of baseline design and services support for arbitrary building blocks that will customize a particular platform firmware image to the hardware and the intended purpose and market for that hardware. These additional elements include such things as security services, boot device policy management, runtime services, afterlife, firmware storage, user interface, firmware integrity services, manageability support, legacy compatibility and boot/resume paths. # ?' |, s; @5 B* z6 Q9 j9 Z
- H9 o9 H9 r. z! g/ SInteroperability and Component Specifications ( [; A, u' J ]6 e
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These additional specifications describe in greater depth the functional components that complement the PEI and DXE Foundations and that are also architectural in the Framework design. "Architectural" in this context implies that the functional components provide services that may always be assumed to be present by any code designed and written to operate across a range of platforms that use firmware based on the Framework design. # ]; z/ h# G) [2 {$ t I3 Z; y
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All specifications are available as PDF files0 ]6 F* W n5 ]3 G* N {' V! Z
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Zip file containing all PDF files (ZIP 11MB)
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Intel® Platform Innovation Framework for EFI Architecture Specification (PDF 893KB) ! V. r7 O2 l- H. A- {# ?7 c
ACPI Specification v0.90 (PDF 212KB)
: R. w- n# k. J. q- j# HACPI Specification v0.91 (PDF 246KB) B: Q, `! f2 `1 ?% f, H
ACPI Table Storage Specification v0.90 (PDF 139KB)
% P% @5 g% j: xACPI Table Storage Specification v0.91 (PDF 190KB) 2 c9 M. F- m& a. C* U9 A
Boot Script Specification v0.9 (PDF 200KB)
3 C5 h2 E" ]5 e2 P' s! }Boot Script Specification v0.91 (PDF 275KB) ' m6 s3 b! |$ o
Cache Subclass Specification (PDF 224KB)
5 Y* P0 y+ k& E" r, yCapsule Specification (PDF 270KB)
4 O& g4 s7 N% M; M! u5 |( T9 G) O" jCompatibility Support Module Specification v0.96 (PDF 547KB) 2 k: r$ ?$ A# K2 P) U
Compatibility Support Module Specification v0.97 (PDF 576KB) , z2 t/ g) [9 {2 Q: M3 v
CPU I/O Protocol Specification (PDF 205KB) 3 p0 Q' L* P u, H$ Q J
Data Hub Specification (PDF 177KB)
& D# P+ Y( q! NData Hub Subclass Design Guide (PDF 156KB) 6 j+ s1 g) B: x8 N: s
Driver Execution Environment Core Interface Specification (DXE CIS)** v0.9 (PDF 1.05MB)
8 i5 q% K4 D6 k( \$ h. |$ p& XDriver Execution Environment Core Interface Specification (DXE CIS)** v0.91 (PDF 1.07MB)
. S, [: N' I" q, A+ f0 yFirmware File System Specification (PDF 237KB)
3 D8 ]; O/ u9 oFirmware Volume Block Specification (PDF 197KB)
8 f! h3 N7 a. f$ VFirmware Volume Specification (PDF 403KB)
' Y# O( w4 n" p/ v+ }Hand-Off Block (HOB) Specification (PDF 231KB)
9 `# l2 m* p% b" {Hot-Plug PCI Initialization Protocol Specification (PDF 108KB)
" |( X: j/ e) h+ U' N: WHuman Interface Infrastructure Specification v0.9 (PDF 597KB)
( B2 x4 U! k5 v8 M* i& w( t4 WHuman Interface Infrastructure Specification v0.91 (PDF 800KB)
Q* B- `2 ~0 k8 p2 d, r2 KHuman Interface Infrastructure Specification v0.92 (PDF 764KB) + M% m% W o8 T5 O; V- M O
IDE Controller Initialization Protocol Specification (PDF 139KB) * ~: T; E5 w4 d* J' l& a, M5 i
Memory Subclass Specification (PDF 397KB) . {4 y+ z+ K* ^( x q6 |: m
Miscellaneous Subclass Specification (PDF 490KB) * l* x" g8 \5 k3 f& C+ x4 P
PCI Host Bridge Resource Allocation Protocol Specification (PDF 212KB)
' W# c' u# l- jPCI Platform Support Specification (PDF 115KB)
: F, q3 n# y- P7 B( ?5 o2 UPlatform IDE Initialization Protocol Specification (PDF 83KB) 2 i; B# b5 V1 Y+ [, t3 L; h# t
Pre-EFI Initialization Core Interface Specification (PEI CIS)** v0.9 (PDF 881KB)
- z' n7 b5 O/ C& \ ]) HPre-EFI Initialization Core Interface Specification (PEI CIS)** v0.91 (PDF 841KB)
. w2 w4 k: o' h+ XProcessor Subclass Specification (PDF 314KB) % \% z$ D& i% r/ U
Recovery Specification (PDF 225KB)
. v* [+ N0 m5 C+ [- ?S3 Resume Boot Path Specification (PDF 173KB) ! B" V) F: g* i- R' R5 g
SMBus Host Controller Protocol Specification (PDF 198KB) 1 h; z, V5 h& G2 S- d
SMBus PPI Specification (PDF 188KB) 1 X. s) V# Z' `; x0 _/ ~. G( T+ Z$ E/ W
Status Codes Specification v0.9 (PDF 682KB)
# [6 ]9 Q0 L' V9 S! z* x8 TStatus Codes Specification v0.92 (PDF 523KB) . r' V( X; u: X
System Management Mode Core Interface Specification (SMM CIS) v0.9 (PDF 713KB)
# a9 s5 O6 B; U" P6 h% y2 BSystem Management Mode Core Interface Specification (SMM CIS) v0.91 (PDF 646KB) |
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